Merge pull request #14699 from jeromecoutant/PR_ASTYLE

STM32 astyle format

Author: 0xc0170

connectivity/drivers/emac/TARGET_STM/TARGET_STM32H7/TARGET_PORTENTA_H7/stm32h7_eth_init.c

@@ -61,14 +61,13 @@
 void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
 {
     GPIO_InitTypeDef GPIO_InitStruct;
-    if(heth->Instance == ETH)
-    {
+    if (heth->Instance == ETH) {
         enableEthPowerSupply();
-        
-        #if !(defined(DUAL_CORE) && defined(CORE_CM4))
+
+#if !(defined(DUAL_CORE) && defined(CORE_CM4))
         /* Disable DCache for STM32H7 family */
         SCB_DisableDCache();
-        #endif
+#endif
 
         /* GPIO Ports Clock Enable */
         __HAL_RCC_GPIOA_CLK_ENABLE();
@@ -118,21 +117,21 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
         PC4     ------> ETH_RXD0
         PC5     ------> ETH_RXD1
         */
-        GPIO_InitStruct.Pin = ETH_TX_EN_Pin|ETH_TXD1_Pin|ETH_TXD0_Pin;
+        GPIO_InitStruct.Pin = ETH_TX_EN_Pin | ETH_TXD1_Pin | ETH_TXD0_Pin;
         GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
         GPIO_InitStruct.Pull = GPIO_NOPULL;
         GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
         GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
         HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
 
-        GPIO_InitStruct.Pin = ETH_MDC_SAI4_D1_Pin|ETH_RXD0_Pin|ETH_RXD1_Pin;
+        GPIO_InitStruct.Pin = ETH_MDC_SAI4_D1_Pin | ETH_RXD0_Pin | ETH_RXD1_Pin;
         GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
         GPIO_InitStruct.Pull = GPIO_NOPULL;
         GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
         GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
         HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
 
-        GPIO_InitStruct.Pin = ETH_MDIO_Pin|ETH_REF_CLK_Pin|ETH_CRS_DV_Pin;
+        GPIO_InitStruct.Pin = ETH_MDIO_Pin | ETH_REF_CLK_Pin | ETH_CRS_DV_Pin;
         GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
         GPIO_InitStruct.Pull = GPIO_NOPULL;
         GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
@@ -146,8 +145,7 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
  */
 void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)
 {
-    if(heth->Instance == ETH)
-    {
+    if (heth->Instance == ETH) {
         /* Peripheral clock disable */
         __HAL_RCC_ETH1MAC_CLK_DISABLE();
         __HAL_RCC_ETH1TX_CLK_DISABLE();
@@ -164,11 +162,11 @@ void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)
         PC4     ------> ETH_RXD0
         PC5     ------> ETH_RXD1
         */
-        HAL_GPIO_DeInit(GPIOG, ETH_TX_EN_Pin|ETH_TXD1_Pin|ETH_TXD0_Pin);
+        HAL_GPIO_DeInit(GPIOG, ETH_TX_EN_Pin | ETH_TXD1_Pin | ETH_TXD0_Pin);
 
-        HAL_GPIO_DeInit(GPIOC, ETH_MDC_SAI4_D1_Pin|ETH_RXD0_Pin|ETH_RXD1_Pin);
+        HAL_GPIO_DeInit(GPIOC, ETH_MDC_SAI4_D1_Pin | ETH_RXD0_Pin | ETH_RXD1_Pin);
 
-        HAL_GPIO_DeInit(GPIOA, ETH_MDIO_Pin|ETH_REF_CLK_Pin|ETH_CRS_DV_Pin);
+        HAL_GPIO_DeInit(GPIOA, ETH_MDIO_Pin | ETH_REF_CLK_Pin | ETH_CRS_DV_Pin);
 
         HAL_GPIO_WritePin(GPIOJ, GPIO_PIN_15, 0);
     }

targets/TARGET_STM/TARGET_STM32F0/TARGET_STM32F070xB/system_clock.c

@@ -95,7 +95,7 @@ MBED_WEAK uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
     //Select HSI as system clock source to allow modification of the PLL configuration
     RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
     RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI;
-    if(HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
+    if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
         return 0; // FAIL
     }
 

targets/TARGET_STM/TARGET_STM32F0/TARGET_STM32F072xB/system_clock.c

@@ -95,7 +95,7 @@ MBED_WEAK uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
     //Select HSI as system clock source to allow modification of the PLL configuration
     RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
     RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI;
-    if(HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
+    if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
         return 0; // FAIL
     }
 

targets/TARGET_STM/TARGET_STM32F0/TARGET_STM32F091xC/system_clock.c

@@ -95,7 +95,7 @@ MBED_WEAK uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
     //Select HSI as system clock source to allow modification of the PLL configuration
     RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
     RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI;
-    if(HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
+    if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
         return 0; // FAIL
     }
 

targets/TARGET_STM/TARGET_STM32F0/cmsis_nvic.c

@@ -18,24 +18,26 @@
 
 #define NVIC_USER_IRQ_OFFSET  16
 
-void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
     int i;
 
     // Copy and switch to dynamic vectors if first time called
     if ((SYSCFG->CFGR1 & SYSCFG_CFGR1_MEM_MODE) != SYSCFG_CFGR1_MEM_MODE) {
         uint32_t *old_vectors = (uint32_t *)NVIC_FLASH_VECTOR_ADDRESS;
         for (i = 0; i < NVIC_NUM_VECTORS; i++) {
-            *((uint32_t *)(NVIC_RAM_VECTOR_ADDRESS + (i*4))) = old_vectors[i];
+            *((uint32_t *)(NVIC_RAM_VECTOR_ADDRESS + (i * 4))) = old_vectors[i];
         }
         SYSCFG->CFGR1 |= SYSCFG_CFGR1_MEM_MODE; // Embedded SRAM mapped at 0x00000000
     }
 
     // Set the vector
-    *((uint32_t *)(NVIC_RAM_VECTOR_ADDRESS + (IRQn*4) + (NVIC_USER_IRQ_OFFSET*4))) = vector;
+    *((uint32_t *)(NVIC_RAM_VECTOR_ADDRESS + (IRQn * 4) + (NVIC_USER_IRQ_OFFSET * 4))) = vector;
 }
 
-uint32_t NVIC_GetVector(IRQn_Type IRQn) {
-    uint32_t *vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
+uint32_t NVIC_GetVector(IRQn_Type IRQn)
+{
+    uint32_t *vectors = (uint32_t *)NVIC_RAM_VECTOR_ADDRESS;
     // Return the vector
     return vectors[IRQn + 16];
 }

targets/TARGET_STM/TARGET_STM32F0/us_ticker_data.h

@@ -17,7 +17,7 @@
 #define __US_TICKER_DATA_H
 
 #ifdef __cplusplus
- extern "C" {
+extern "C" {
 #endif
 
 #include "stm32f0xx.h"

targets/TARGET_STM/TARGET_STM32F3/us_ticker_data.h

@@ -18,13 +18,13 @@
 #define __US_TICKER_DATA_H
 
 #ifdef __cplusplus
- extern "C" {
+extern "C" {
 #endif
 
 #include "stm32f3xx.h"
 #include "stm32f3xx_ll_tim.h"
 #include "cmsis_nvic.h"
-   
+
 #define TIM_MST      TIM2
 #define TIM_MST_IRQ  TIM2_IRQn
 #define TIM_MST_RCC  __HAL_RCC_TIM2_CLK_ENABLE()

targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/system_clock.c

@@ -106,8 +106,7 @@ MBED_WEAK uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
     HAL_RCC_GetOscConfig(&RCC_OscInitStruct);
 
     /* PLL could be already configured by bootlader */
-    if (RCC_OscInitStruct.PLL.PLLState != RCC_PLL_ON)
-    {
+    if (RCC_OscInitStruct.PLL.PLLState != RCC_PLL_ON) {
         /* Enable HSE oscillator and activate PLL with HSE as source */
         RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSE;
         if (bypass == 0) {

targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_DISCO_F413ZH/TargetInit.c

@@ -15,7 +15,8 @@
 
 #include "stm32f4xx.h"
 
-void TargetBSP_Init(void) {
+void TargetBSP_Init(void)
+{
     /* In DISCO_F413ZH board, Arduino connector and Wifi embeded module are sharing the same SPI pins */
     /* We need to set the default SPI SS pin for the Wifi module to the inactive state i.e. 1 */
     /* See board User Manual: WIFI_SPI_CS = PG_11*/

targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/TARGET_NUCLEO_F429ZI/PinNames.h

@@ -290,7 +290,7 @@ typedef enum {
     D69 = PF_1,
     D70 = PF_2,
     D71 = PA_7,
-    
+
     // STDIO for console print
 #ifdef MBED_CONF_TARGET_STDIO_UART_TX
     CONSOLE_TX = MBED_CONF_TARGET_STDIO_UART_TX,
@@ -394,4 +394,3 @@ typedef enum {
 #endif
 
 #endif
-