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STM32L0 warning compilation
[-Wparentheses-equality]
1 parent 7d05f22 commit daf8d11

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+14
-14
lines changed

1 file changed

+14
-14
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targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_tim.c

Lines changed: 14 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -394,11 +394,11 @@ HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pDat
394394
/* Check the parameters */
395395
assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
396396

397-
if((htim->State == HAL_TIM_STATE_BUSY))
397+
if(htim->State == HAL_TIM_STATE_BUSY)
398398
{
399399
return HAL_BUSY;
400400
}
401-
else if((htim->State == HAL_TIM_STATE_READY))
401+
else if(htim->State == HAL_TIM_STATE_READY)
402402
{
403403
if((pData == 0U ) && (Length > 0U))
404404
{
@@ -765,11 +765,11 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel
765765
/* Check the parameters */
766766
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
767767

768-
if((htim->State == HAL_TIM_STATE_BUSY))
768+
if(htim->State == HAL_TIM_STATE_BUSY)
769769
{
770770
return HAL_BUSY;
771771
}
772-
else if((htim->State == HAL_TIM_STATE_READY))
772+
else if(htim->State == HAL_TIM_STATE_READY)
773773
{
774774
if(((uint32_t)pData == 0U ) && (Length > 0U))
775775
{
@@ -1243,11 +1243,11 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe
12431243
/* Check the parameters */
12441244
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
12451245

1246-
if((htim->State == HAL_TIM_STATE_BUSY))
1246+
if(htim->State == HAL_TIM_STATE_BUSY)
12471247
{
12481248
return HAL_BUSY;
12491249
}
1250-
else if((htim->State == HAL_TIM_STATE_READY))
1250+
else if(htim->State == HAL_TIM_STATE_READY)
12511251
{
12521252
if(((uint32_t)pData == 0U ) && (Length > 0U))
12531253
{
@@ -1714,11 +1714,11 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel
17141714
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
17151715
assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
17161716

1717-
if((htim->State == HAL_TIM_STATE_BUSY))
1717+
if(htim->State == HAL_TIM_STATE_BUSY)
17181718
{
17191719
return HAL_BUSY;
17201720
}
1721-
else if((htim->State == HAL_TIM_STATE_READY))
1721+
else if(htim->State == HAL_TIM_STATE_READY)
17221722
{
17231723
if((pData == 0U ) && (Length > 0U))
17241724
{
@@ -2505,11 +2505,11 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch
25052505
/* Check the parameters */
25062506
assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
25072507

2508-
if((htim->State == HAL_TIM_STATE_BUSY))
2508+
if(htim->State == HAL_TIM_STATE_BUSY)
25092509
{
25102510
return HAL_BUSY;
25112511
}
2512-
else if((htim->State == HAL_TIM_STATE_READY))
2512+
else if(htim->State == HAL_TIM_STATE_READY)
25132513
{
25142514
if((((pData1 == 0U) || (pData2 == 0U) )) && (Length > 0U))
25152515
{
@@ -3227,11 +3227,11 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t
32273227
assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
32283228
assert_param(IS_TIM_DMA_LENGTH(BurstLength));
32293229

3230-
if((htim->State == HAL_TIM_STATE_BUSY))
3230+
if(htim->State == HAL_TIM_STATE_BUSY)
32313231
{
32323232
return HAL_BUSY;
32333233
}
3234-
else if((htim->State == HAL_TIM_STATE_READY))
3234+
else if(htim->State == HAL_TIM_STATE_READY)
32353235
{
32363236
if((BurstBuffer == 0U ) && (BurstLength > 0U))
32373237
{
@@ -3429,11 +3429,11 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B
34293429
assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
34303430
assert_param(IS_TIM_DMA_LENGTH(BurstLength));
34313431

3432-
if((htim->State == HAL_TIM_STATE_BUSY))
3432+
if(htim->State == HAL_TIM_STATE_BUSY)
34333433
{
34343434
return HAL_BUSY;
34353435
}
3436-
else if((htim->State == HAL_TIM_STATE_READY))
3436+
else if(htim->State == HAL_TIM_STATE_READY)
34373437
{
34383438
if((BurstBuffer == 0U ) && (BurstLength > 0U))
34393439
{

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