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[NUCLEO_F103RB] Correction in SPI clock setting.
1 parent adab2d9 commit ddce5e7

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  • libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB

1 file changed

+2
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libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/spi_api.c

Lines changed: 2 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -57,8 +57,6 @@ static const PinMap PinMap_SPI_SCLK[] = {
5757
// Only used in Slave mode
5858
static const PinMap PinMap_SPI_SSEL[] = {
5959
{PB_6, SPI_1, STM_PIN_DATA(GPIO_Mode_IN_FLOATING, 0)}, // Generic IO, not real H/W NSS pin
60-
//{PA_4, SPI_1, STM_PIN_DATA(GPIO_Mode_IN_FLOATING, 0)},
61-
//{PA_15, SPI_1, STM_PIN_DATA(GPIO_Mode_IN_FLOATING, 1)}, // Remap
6260
{NC, NC, 0}
6361
};
6462

@@ -102,9 +100,6 @@ void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel
102100
if (obj->spi == SPI_1) {
103101
RCC_APB2PeriphClockCmd(RCC_APB2Periph_SPI1, ENABLE);
104102
}
105-
if (obj->spi == SPI_2) {
106-
RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI2, ENABLE);
107-
}
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109104
// Configure the SPI pins
110105
pinmap_pinout(mosi, PinMap_SPI_MOSI);
@@ -115,7 +110,7 @@ void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel
115110
obj->bits = SPI_DataSize_8b;
116111
obj->cpol = SPI_CPOL_Low;
117112
obj->cpha = SPI_CPHA_1Edge;
118-
obj->br_presc = SPI_BaudRatePrescaler_64; // Closest to 1MHz (72MHz/64 = 1.125MHz)
113+
obj->br_presc = SPI_BaudRatePrescaler_256; // 1MHz
119114

120115
if (ssel == NC) { // Master
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obj->mode = SPI_Mode_Master;
@@ -176,11 +171,8 @@ void spi_format(spi_t *obj, int bits, int mode, int slave) {
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}
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178173
void spi_frequency(spi_t *obj, int hz) {
179-
// Get SPI clock frequency
180-
uint32_t PCLK = SystemCoreClock >> 1;
181-
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// Choose the baud rate divisor (between 2 and 256)
183-
uint32_t divisor = PCLK / hz;
175+
uint32_t divisor = SystemCoreClock / hz;
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185177
// Find the nearest power-of-2
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divisor = (divisor > 0 ? divisor-1 : 0);

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