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| 1 | +/* |
| 2 | + * Copyright (c) 2022, Nuvoton Technology Corporation |
| 3 | + * |
| 4 | + * SPDX-License-Identifier: Apache-2.0 |
| 5 | + * |
| 6 | + * Licensed under the Apache License, Version 2.0 (the "License"); |
| 7 | + * you may not use this file except in compliance with the License. |
| 8 | + * You may obtain a copy of the License at |
| 9 | + * |
| 10 | + * http://www.apache.org/licenses/LICENSE-2.0 |
| 11 | + * |
| 12 | + * Unless required by applicable law or agreed to in writing, software |
| 13 | + * distributed under the License is distributed on an "AS IS" BASIS, |
| 14 | + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 15 | + * See the License for the specific language governing permissions and |
| 16 | + * limitations under the License. |
| 17 | + */ |
| 18 | + |
| 19 | +#ifndef MBED_PERIPHERALNAMES_H |
| 20 | +#define MBED_PERIPHERALNAMES_H |
| 21 | + |
| 22 | +#include "cmsis.h" |
| 23 | +#include "PinNames.h" |
| 24 | + |
| 25 | +#ifdef __cplusplus |
| 26 | +extern "C" { |
| 27 | +#endif |
| 28 | + |
| 29 | +// NOTE: Check all module base addresses (XXX_BASE in BSP) for free bit fields to define module name |
| 30 | +// which encodes module base address and module index/subindex. |
| 31 | +#define NU_MODSUBINDEX_Pos 0 |
| 32 | +#define NU_MODSUBINDEX_Msk (0x1Ful << NU_MODSUBINDEX_Pos) |
| 33 | +#define NU_MODINDEX_Pos 20 |
| 34 | +#define NU_MODINDEX_Msk (0xFul << NU_MODINDEX_Pos) |
| 35 | + |
| 36 | +#define NU_MODNAME(MODBASE, INDEX, SUBINDEX) ((MODBASE) | ((INDEX) << NU_MODINDEX_Pos) | ((SUBINDEX) << NU_MODSUBINDEX_Pos)) |
| 37 | +#define NU_MODBASE(MODNAME) ((MODNAME) & ~(NU_MODINDEX_Msk | NU_MODSUBINDEX_Msk)) |
| 38 | +#define NU_MODINDEX(MODNAME) (((MODNAME) & NU_MODINDEX_Msk) >> NU_MODINDEX_Pos) |
| 39 | +#define NU_MODSUBINDEX(MODNAME) (((MODNAME) & NU_MODSUBINDEX_Msk) >> NU_MODSUBINDEX_Pos) |
| 40 | + |
| 41 | +#if 0 |
| 42 | +typedef enum { |
| 43 | + GPIO_A = (int) NU_MODNAME(GPIOA_BASE, 0, 0), |
| 44 | + GPIO_B = (int) NU_MODNAME(GPIOB_BASE, 1, 0), |
| 45 | + GPIO_C = (int) NU_MODNAME(GPIOC_BASE, 2, 0), |
| 46 | + GPIO_D = (int) NU_MODNAME(GPIOD_BASE, 3, 0), |
| 47 | + GPIO_E = (int) NU_MODNAME(GPIOE_BASE, 4, 0), |
| 48 | + GPIO_F = (int) NU_MODNAME(GPIOF_BASE, 5, 0), |
| 49 | + GPIO_G = (int) NU_MODNAME(GPIOG_BASE, 6, 0), |
| 50 | + GPIO_H = (int) NU_MODNAME(GPIOH_BASE, 7, 0), |
| 51 | + GPIO_I = (int) NU_MODNAME(GPIOI_BASE, 8, 0), |
| 52 | + GPIO_J = (int) NU_MODNAME(GPIOJ_BASE, 9, 0), |
| 53 | +} GPIOName; |
| 54 | +#endif |
| 55 | + |
| 56 | +typedef enum { |
| 57 | + /* EADC0 */ |
| 58 | + ADC_0_0 = (int) NU_MODNAME(EADC0_BASE, 0, 0), |
| 59 | + ADC_0_1 = (int) NU_MODNAME(EADC0_BASE, 0, 1), |
| 60 | + ADC_0_2 = (int) NU_MODNAME(EADC0_BASE, 0, 2), |
| 61 | + ADC_0_3 = (int) NU_MODNAME(EADC0_BASE, 0, 3), |
| 62 | + ADC_0_4 = (int) NU_MODNAME(EADC0_BASE, 0, 4), |
| 63 | + ADC_0_5 = (int) NU_MODNAME(EADC0_BASE, 0, 5), |
| 64 | + ADC_0_6 = (int) NU_MODNAME(EADC0_BASE, 0, 6), |
| 65 | + ADC_0_7 = (int) NU_MODNAME(EADC0_BASE, 0, 7), |
| 66 | + ADC_0_8 = (int) NU_MODNAME(EADC0_BASE, 0, 8), |
| 67 | + ADC_0_9 = (int) NU_MODNAME(EADC0_BASE, 0, 9), |
| 68 | + ADC_0_10 = (int) NU_MODNAME(EADC0_BASE, 0, 10), |
| 69 | + ADC_0_11 = (int) NU_MODNAME(EADC0_BASE, 0, 11), |
| 70 | + ADC_0_12 = (int) NU_MODNAME(EADC0_BASE, 0, 12), |
| 71 | + ADC_0_13 = (int) NU_MODNAME(EADC0_BASE, 0, 13), |
| 72 | + ADC_0_14 = (int) NU_MODNAME(EADC0_BASE, 0, 14), |
| 73 | + ADC_0_15 = (int) NU_MODNAME(EADC0_BASE, 0, 15), |
| 74 | + |
| 75 | + /* EADC1 */ |
| 76 | + ADC_1_0 = (int) NU_MODNAME(EADC1_BASE, 1, 0), |
| 77 | + ADC_1_1 = (int) NU_MODNAME(EADC1_BASE, 1, 1), |
| 78 | + ADC_1_2 = (int) NU_MODNAME(EADC1_BASE, 1, 2), |
| 79 | + ADC_1_3 = (int) NU_MODNAME(EADC1_BASE, 1, 3), |
| 80 | + ADC_1_4 = (int) NU_MODNAME(EADC1_BASE, 1, 4), |
| 81 | + ADC_1_5 = (int) NU_MODNAME(EADC1_BASE, 1, 5), |
| 82 | + ADC_1_6 = (int) NU_MODNAME(EADC1_BASE, 1, 6), |
| 83 | + ADC_1_7 = (int) NU_MODNAME(EADC1_BASE, 1, 7), |
| 84 | + ADC_1_8 = (int) NU_MODNAME(EADC1_BASE, 1, 8), |
| 85 | + ADC_1_9 = (int) NU_MODNAME(EADC1_BASE, 1, 9), |
| 86 | + ADC_1_10 = (int) NU_MODNAME(EADC1_BASE, 1, 10), |
| 87 | + ADC_1_11 = (int) NU_MODNAME(EADC1_BASE, 1, 11), |
| 88 | + ADC_1_12 = (int) NU_MODNAME(EADC1_BASE, 1, 12), |
| 89 | + ADC_1_13 = (int) NU_MODNAME(EADC1_BASE, 1, 13), |
| 90 | + ADC_1_14 = (int) NU_MODNAME(EADC1_BASE, 1, 14), |
| 91 | + ADC_1_15 = (int) NU_MODNAME(EADC1_BASE, 1, 15), |
| 92 | + |
| 93 | + /* EADC2 */ |
| 94 | + ADC_2_0 = (int) NU_MODNAME(EADC2_BASE, 2, 0), |
| 95 | + ADC_2_1 = (int) NU_MODNAME(EADC2_BASE, 2, 1), |
| 96 | + ADC_2_2 = (int) NU_MODNAME(EADC2_BASE, 2, 2), |
| 97 | + ADC_2_3 = (int) NU_MODNAME(EADC2_BASE, 2, 3), |
| 98 | + ADC_2_4 = (int) NU_MODNAME(EADC2_BASE, 2, 4), |
| 99 | + ADC_2_5 = (int) NU_MODNAME(EADC2_BASE, 2, 5), |
| 100 | + ADC_2_6 = (int) NU_MODNAME(EADC2_BASE, 2, 6), |
| 101 | + ADC_2_7 = (int) NU_MODNAME(EADC2_BASE, 2, 7), |
| 102 | + ADC_2_8 = (int) NU_MODNAME(EADC2_BASE, 2, 8), |
| 103 | + ADC_2_9 = (int) NU_MODNAME(EADC2_BASE, 2, 9), |
| 104 | + ADC_2_10 = (int) NU_MODNAME(EADC2_BASE, 2, 10), |
| 105 | + ADC_2_11 = (int) NU_MODNAME(EADC2_BASE, 2, 11), |
| 106 | + ADC_2_12 = (int) NU_MODNAME(EADC2_BASE, 2, 12), |
| 107 | + ADC_2_13 = (int) NU_MODNAME(EADC2_BASE, 2, 13), |
| 108 | + ADC_2_14 = (int) NU_MODNAME(EADC2_BASE, 2, 14), |
| 109 | + ADC_2_15 = (int) NU_MODNAME(EADC2_BASE, 2, 15), |
| 110 | +} ADCName; |
| 111 | + |
| 112 | +typedef enum { |
| 113 | + DAC_0_0 = (int) NU_MODNAME(DAC0_BASE, 0, 0), |
| 114 | + DAC_1_0 = (int) NU_MODNAME(DAC1_BASE, 1, 0), |
| 115 | +} DACName; |
| 116 | + |
| 117 | +typedef enum { |
| 118 | + UART_0 = (int) NU_MODNAME(UART0_BASE, 0, 0), |
| 119 | + UART_1 = (int) NU_MODNAME(UART1_BASE, 1, 0), |
| 120 | + UART_2 = (int) NU_MODNAME(UART2_BASE, 2, 0), |
| 121 | + UART_3 = (int) NU_MODNAME(UART3_BASE, 3, 0), |
| 122 | + UART_4 = (int) NU_MODNAME(UART4_BASE, 4, 0), |
| 123 | + UART_5 = (int) NU_MODNAME(UART5_BASE, 5, 0), |
| 124 | + UART_6 = (int) NU_MODNAME(UART6_BASE, 6, 0), |
| 125 | + UART_7 = (int) NU_MODNAME(UART7_BASE, 7, 0), |
| 126 | + UART_8 = (int) NU_MODNAME(UART8_BASE, 8, 0), |
| 127 | + UART_9 = (int) NU_MODNAME(UART9_BASE, 9, 0), |
| 128 | + // NOTE: board-specific |
| 129 | +#if defined(MBED_CONF_TARGET_USB_UART) |
| 130 | + USB_UART = MBED_CONF_TARGET_USB_UART, |
| 131 | +#else |
| 132 | + USB_UART = NC, |
| 133 | +#endif |
| 134 | +#if defined(MBED_CONF_TARGET_STDIO_UART) |
| 135 | + STDIO_UART = MBED_CONF_TARGET_STDIO_UART, |
| 136 | +#else |
| 137 | + STDIO_UART = USB_UART, |
| 138 | +#endif |
| 139 | +} UARTName; |
| 140 | + |
| 141 | +typedef enum { |
| 142 | + SPI_0 = (int) NU_MODNAME(SPI0_BASE, 0, 0), |
| 143 | + SPI_1 = (int) NU_MODNAME(SPI1_BASE, 1, 0), |
| 144 | + SPI_2 = (int) NU_MODNAME(SPI2_BASE, 2, 0), |
| 145 | + SPI_3 = (int) NU_MODNAME(SPI3_BASE, 3, 0), |
| 146 | + SPI_4 = (int) NU_MODNAME(SPI4_BASE, 4, 0), |
| 147 | + SPI_5 = (int) NU_MODNAME(SPI5_BASE, 5, 0), |
| 148 | + SPI_6 = (int) NU_MODNAME(SPI6_BASE, 6, 0), |
| 149 | + SPI_7 = (int) NU_MODNAME(SPI7_BASE, 7, 0), |
| 150 | + SPI_8 = (int) NU_MODNAME(SPI8_BASE, 8, 0), |
| 151 | + SPI_9 = (int) NU_MODNAME(SPI9_BASE, 9, 0), |
| 152 | + SPI_10 = (int) NU_MODNAME(SPI10_BASE, 10, 0), |
| 153 | + |
| 154 | + /* No SPI11/12 H/W, degrade QSPI0/1 H/W to SPI_11/12 for standard SPI usage */ |
| 155 | + SPI_11 = (int) NU_MODNAME(QSPI0_BASE, 11, 0), |
| 156 | + SPI_12 = (int) NU_MODNAME(QSPI1_BASE, 12, 0), |
| 157 | +} SPIName; |
| 158 | + |
| 159 | +typedef enum { |
| 160 | + I2C_0 = (int) NU_MODNAME(I2C0_BASE, 0, 0), |
| 161 | + I2C_1 = (int) NU_MODNAME(I2C1_BASE, 1, 0), |
| 162 | + I2C_2 = (int) NU_MODNAME(I2C2_BASE, 2, 0), |
| 163 | + I2C_3 = (int) NU_MODNAME(I2C3_BASE, 3, 0), |
| 164 | + I2C_4 = (int) NU_MODNAME(I2C4_BASE, 4, 0), |
| 165 | +} I2CName; |
| 166 | + |
| 167 | +typedef enum { |
| 168 | + PWM_0_0 = (int) NU_MODNAME(EPWM0_BASE, 0, 0), |
| 169 | + PWM_0_1 = (int) NU_MODNAME(EPWM0_BASE, 0, 1), |
| 170 | + PWM_0_2 = (int) NU_MODNAME(EPWM0_BASE, 0, 2), |
| 171 | + PWM_0_3 = (int) NU_MODNAME(EPWM0_BASE, 0, 3), |
| 172 | + PWM_0_4 = (int) NU_MODNAME(EPWM0_BASE, 0, 4), |
| 173 | + PWM_0_5 = (int) NU_MODNAME(EPWM0_BASE, 0, 5), |
| 174 | + |
| 175 | + PWM_1_0 = (int) NU_MODNAME(EPWM1_BASE, 1, 0), |
| 176 | + PWM_1_1 = (int) NU_MODNAME(EPWM1_BASE, 1, 1), |
| 177 | + PWM_1_2 = (int) NU_MODNAME(EPWM1_BASE, 1, 2), |
| 178 | + PWM_1_3 = (int) NU_MODNAME(EPWM1_BASE, 1, 3), |
| 179 | + PWM_1_4 = (int) NU_MODNAME(EPWM1_BASE, 1, 4), |
| 180 | + PWM_1_5 = (int) NU_MODNAME(EPWM1_BASE, 1, 5), |
| 181 | +} PWMName; |
| 182 | + |
| 183 | +typedef enum { |
| 184 | + TIMER_0 = (int) NU_MODNAME(TIMER0_BASE, 0, 0), |
| 185 | + TIMER_1 = (int) NU_MODNAME(TIMER1_BASE, 1, 0), |
| 186 | + TIMER_2 = (int) NU_MODNAME(TIMER2_BASE, 2, 0), |
| 187 | + TIMER_3 = (int) NU_MODNAME(TIMER3_BASE, 3, 0), |
| 188 | +} TIMERName; |
| 189 | + |
| 190 | +typedef enum { |
| 191 | + RTC_0 = (int) NU_MODNAME(RTC_BASE, 0, 0), |
| 192 | +} RTCName; |
| 193 | + |
| 194 | +typedef enum { |
| 195 | + DMA_0 = (int) NU_MODNAME(PDMA0_BASE, 0, 0), |
| 196 | + DMA_1 = (int) NU_MODNAME(PDMA1_BASE, 1, 0), |
| 197 | +} DMAName; |
| 198 | + |
| 199 | +typedef enum { |
| 200 | + SD_0 = (int) NU_MODNAME(SDH0_BASE, 0, 0), |
| 201 | + SD_1 = (int) NU_MODNAME(SDH1_BASE, 1, 0), |
| 202 | +} SDName; |
| 203 | + |
| 204 | +typedef enum { |
| 205 | + CAN_0 = (int) NU_MODNAME(CANFD0_BASE, 0, 0), |
| 206 | + CAN_1 = (int) NU_MODNAME(CANFD1_BASE, 1, 0), |
| 207 | + CAN_2 = (int) NU_MODNAME(CANFD2_BASE, 2, 0), |
| 208 | + CAN_3 = (int) NU_MODNAME(CANFD3_BASE, 3, 0), |
| 209 | +} CANName; |
| 210 | + |
| 211 | +typedef enum { |
| 212 | + TRNG_0 = (int) NU_MODNAME(TRNG_BASE, 0, 0), |
| 213 | +} TRNGName; |
| 214 | + |
| 215 | +#ifdef __cplusplus |
| 216 | +} |
| 217 | +#endif |
| 218 | + |
| 219 | +#endif |
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