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targets/TARGET_STM/TARGET_STM32F4
TARGET_STM32F412xG/TARGET_NUCLEO_F412ZG
TARGET_STM32F413xH/TARGET_DISCO_F413ZH Expand file tree Collapse file tree 2 files changed +12
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lines changed Original file line number Diff line number Diff line change @@ -176,11 +176,13 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
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}
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/* Select PLLSAI output as USB clock source */
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+ PeriphClkInitStruct .PeriphClockSelection = RCC_PERIPHCLK_CLK48 ;
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PeriphClkInitStruct .PLLI2S .PLLI2SM = 8 ;
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PeriphClkInitStruct .PLLI2S .PLLI2SQ = 4 ;
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PeriphClkInitStruct .PLLI2S .PLLI2SN = 192 ;
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- PeriphClkInitStruct .PeriphClockSelection = RCC_PERIPHCLK_CLK48 ;
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+ PeriphClkInitStruct .PLLI2S . PLLI2SR = 2 ;
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PeriphClkInitStruct .Clk48ClockSelection = RCC_CLK48CLKSOURCE_PLLI2SQ ;
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+ PeriphClkInitStruct .PLLI2SSelection = RCC_PLLI2SCLKSOURCE_PLLSRC ;
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HAL_RCCEx_PeriphCLKConfig (& PeriphClkInitStruct );
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@@ -241,11 +243,13 @@ uint8_t SetSysClock_PLL_HSI(void)
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}
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/* Select PLLSAI output as USB clock source */
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+ PeriphClkInitStruct .PeriphClockSelection = RCC_PERIPHCLK_CLK48 ;
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PeriphClkInitStruct .PLLI2S .PLLI2SM = 16 ;
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PeriphClkInitStruct .PLLI2S .PLLI2SN = 192 ;
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PeriphClkInitStruct .PLLI2S .PLLI2SQ = 4 ;
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- PeriphClkInitStruct .PeriphClockSelection = RCC_PERIPHCLK_CLK48 ;
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+ PeriphClkInitStruct .PLLI2S . PLLI2SR = 2 ;
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PeriphClkInitStruct .Clk48ClockSelection = RCC_CLK48CLKSOURCE_PLLI2SQ ;
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+ PeriphClkInitStruct .PLLI2SSelection = RCC_PLLI2SCLKSOURCE_PLLSRC ;
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HAL_RCCEx_PeriphCLKConfig (& PeriphClkInitStruct );
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Original file line number Diff line number Diff line change @@ -177,11 +177,13 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
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}
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/* Select PLLSAI output as USB clock source */
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+ PeriphClkInitStruct .PeriphClockSelection = RCC_PERIPHCLK_CLK48 ;
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PeriphClkInitStruct .PLLI2S .PLLI2SM = 8 ;
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PeriphClkInitStruct .PLLI2S .PLLI2SQ = 4 ;
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PeriphClkInitStruct .PLLI2S .PLLI2SN = 192 ;
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- PeriphClkInitStruct .PeriphClockSelection = RCC_PERIPHCLK_CLK48 ;
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+ PeriphClkInitStruct .PLLI2S . PLLI2SR = 2 ;
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PeriphClkInitStruct .Clk48ClockSelection = RCC_CLK48CLKSOURCE_PLLI2SQ ;
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+ PeriphClkInitStruct .PLLI2SSelection = RCC_PLLI2SCLKSOURCE_PLLSRC ;
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HAL_RCCEx_PeriphCLKConfig (& PeriphClkInitStruct );
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@@ -242,11 +244,13 @@ uint8_t SetSysClock_PLL_HSI(void)
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}
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/* Select PLLI2S output as USB clock source */
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+ PeriphClkInitStruct .PeriphClockSelection = RCC_PERIPHCLK_CLK48 ;
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PeriphClkInitStruct .PLLI2S .PLLI2SM = 16 ;
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PeriphClkInitStruct .PLLI2S .PLLI2SN = 192 ;
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PeriphClkInitStruct .PLLI2S .PLLI2SQ = 4 ;
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- PeriphClkInitStruct .PeriphClockSelection = RCC_PERIPHCLK_CLK48 ;
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+ PeriphClkInitStruct .PLLI2S . PLLI2SR = 2 ;
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PeriphClkInitStruct .Clk48ClockSelection = RCC_CLK48CLKSOURCE_PLLI2SQ ;
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+ PeriphClkInitStruct .PLLI2SSelection = RCC_PLLI2SCLKSOURCE_PLLSRC ;
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HAL_RCCEx_PeriphCLKConfig (& PeriphClkInitStruct );
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