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Commit e005456

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jeromecoutantadbridge
authored andcommitted
STM32F4 : compilation issue
Issue comes only when ST HAL macro USE_FULL_ASSERT is enabled
1 parent 0dfa368 commit e005456

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2 files changed

+12
-4
lines changed

2 files changed

+12
-4
lines changed

targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_NUCLEO_F412ZG/system_clock.c

Lines changed: 6 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -176,11 +176,13 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
176176
}
177177

178178
/* Select PLLSAI output as USB clock source */
179+
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48;
179180
PeriphClkInitStruct.PLLI2S.PLLI2SM = 8;
180181
PeriphClkInitStruct.PLLI2S.PLLI2SQ = 4;
181182
PeriphClkInitStruct.PLLI2S.PLLI2SN = 192;
182-
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48;
183+
PeriphClkInitStruct.PLLI2S.PLLI2SR = 2;
183184
PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48CLKSOURCE_PLLI2SQ;
185+
PeriphClkInitStruct.PLLI2SSelection = RCC_PLLI2SCLKSOURCE_PLLSRC;
184186

185187
HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
186188

@@ -241,11 +243,13 @@ uint8_t SetSysClock_PLL_HSI(void)
241243
}
242244

243245
/* Select PLLSAI output as USB clock source */
246+
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48;
244247
PeriphClkInitStruct.PLLI2S.PLLI2SM = 16;
245248
PeriphClkInitStruct.PLLI2S.PLLI2SN = 192;
246249
PeriphClkInitStruct.PLLI2S.PLLI2SQ = 4;
247-
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48;
250+
PeriphClkInitStruct.PLLI2S.PLLI2SR = 2;
248251
PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48CLKSOURCE_PLLI2SQ;
252+
PeriphClkInitStruct.PLLI2SSelection = RCC_PLLI2SCLKSOURCE_PLLSRC;
249253

250254
HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
251255

targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_DISCO_F413ZH/system_clock.c

Lines changed: 6 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -177,11 +177,13 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
177177
}
178178

179179
/* Select PLLSAI output as USB clock source */
180+
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48;
180181
PeriphClkInitStruct.PLLI2S.PLLI2SM = 8;
181182
PeriphClkInitStruct.PLLI2S.PLLI2SQ = 4;
182183
PeriphClkInitStruct.PLLI2S.PLLI2SN = 192;
183-
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48;
184+
PeriphClkInitStruct.PLLI2S.PLLI2SR = 2;
184185
PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48CLKSOURCE_PLLI2SQ;
186+
PeriphClkInitStruct.PLLI2SSelection = RCC_PLLI2SCLKSOURCE_PLLSRC;
185187

186188
HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
187189

@@ -242,11 +244,13 @@ uint8_t SetSysClock_PLL_HSI(void)
242244
}
243245

244246
/* Select PLLI2S output as USB clock source */
247+
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48;
245248
PeriphClkInitStruct.PLLI2S.PLLI2SM = 16;
246249
PeriphClkInitStruct.PLLI2S.PLLI2SN = 192;
247250
PeriphClkInitStruct.PLLI2S.PLLI2SQ = 4;
248-
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48;
251+
PeriphClkInitStruct.PLLI2S.PLLI2SR = 2;
249252
PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48CLKSOURCE_PLLI2SQ;
253+
PeriphClkInitStruct.PLLI2SSelection = RCC_PLLI2SCLKSOURCE_PLLSRC;
250254

251255
HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
252256

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