Skip to content

Commit e439ad9

Browse files
0xc01700xc0170
authored
Merge pull request #13778 from jeromecoutant/PR_G4-130
STM32G4 update drivers version to CUBE V1.3.0
2 parents ed73a48 + 759a817 commit e439ad9

File tree

214 files changed

+38241
-8046
lines changed

Some content is hidden

Large Commits have some content hidden by default. Use the searchbox below for content that may be hidden.

214 files changed

+38241
-8046
lines changed

‎targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G474xx/TARGET_NUCLEO_G474RE/PeripheralNames.h renamed to ‎targets/TARGET_STM/TARGET_STM32G4/PeripheralNames.h

Lines changed: 39 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -1,19 +1,18 @@
11
/* mbed Microcontroller Library
2-
* Copyright (c) 2016 ARM Limited
3-
* SPDX-License-Identifier: Apache-2.0
2+
* SPDX-License-Identifier: BSD-3-Clause
3+
******************************************************************************
44
*
5-
* Licensed under the Apache License, Version 2.0 (the "License");
6-
* you may not use this file except in compliance with the License.
7-
* You may obtain a copy of the License at
5+
* Copyright (c) 2015-2020 STMicroelectronics.
6+
* All rights reserved.
87
*
9-
* http://www.apache.org/licenses/LICENSE-2.0
8+
* This software component is licensed by ST under BSD 3-Clause license,
9+
* the "License"; You may not use this file except in compliance with the
10+
* License. You may obtain a copy of the License at:
11+
* opensource.org/licenses/BSD-3-Clause
1012
*
11-
* Unless required by applicable law or agreed to in writing, software
12-
* distributed under the License is distributed on an "AS IS" BASIS,
13-
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14-
* See the License for the specific language governing permissions and
15-
* limitations under the License.
13+
******************************************************************************
1614
*/
15+
1716
#ifndef MBED_PERIPHERALNAMES_H
1817
#define MBED_PERIPHERALNAMES_H
1918

@@ -26,25 +25,36 @@ extern "C" {
2625
typedef enum {
2726
ADC_1 = (int)ADC1_BASE,
2827
ADC_2 = (int)ADC2_BASE,
28+
#if defined ADC3_BASE
2929
ADC_3 = (int)ADC3_BASE,
30+
#endif
31+
#if defined ADC4_BASE
3032
ADC_4 = (int)ADC4_BASE,
31-
ADC_5 = (int)ADC5_BASE
33+
#endif
34+
#if defined ADC5_BASE
35+
ADC_5 = (int)ADC5_BASE,
36+
#endif
3237
} ADCName;
3338

3439
typedef enum {
3540
DAC_1 = (int)DAC1_BASE,
41+
#if defined DAC2_BASE
3642
DAC_2 = (int)DAC2_BASE,
43+
#endif
3744
DAC_3 = (int)DAC3_BASE,
45+
#if defined DAC4_BASE
3846
DAC_4 = (int)DAC4_BASE,
39-
47+
#endif
4048
} DACName;
4149

4250
typedef enum {
4351
UART_1 = (int)USART1_BASE,
4452
UART_2 = (int)USART2_BASE,
4553
UART_3 = (int)USART3_BASE,
4654
UART_4 = (int)UART4_BASE,
55+
#if defined UART5_BASE
4756
UART_5 = (int)UART5_BASE,
57+
#endif
4858
LPUART_1 = (int)LPUART1_BASE
4959
} UARTName;
5060

@@ -53,40 +63,54 @@ typedef enum {
5363
SPI_1 = (int)SPI1_BASE,
5464
SPI_2 = (int)SPI2_BASE,
5565
SPI_3 = (int)SPI3_BASE,
66+
#if defined SPI4_BASE
5667
SPI_4 = (int)SPI4_BASE,
68+
#endif
5769
} SPIName;
5870

5971
typedef enum {
6072
I2C_1 = (int)I2C1_BASE,
6173
I2C_2 = (int)I2C2_BASE,
6274
I2C_3 = (int)I2C3_BASE,
75+
#if defined I2C4_BASE
6376
I2C_4 = (int)I2C4_BASE
77+
#endif
6478
} I2CName;
6579

6680
typedef enum {
6781
PWM_1 = (int)TIM1_BASE,
6882
PWM_2 = (int)TIM2_BASE,
6983
PWM_3 = (int)TIM3_BASE,
7084
PWM_4 = (int)TIM4_BASE,
85+
#if defined TIM5_BASE
7186
PWM_5 = (int)TIM5_BASE,
87+
#endif
7288
PWM_6 = (int)TIM6_BASE,
7389
PWM_7 = (int)TIM7_BASE,
7490
PWM_8 = (int)TIM8_BASE,
7591
PWM_15 = (int)TIM15_BASE,
7692
PWM_16 = (int)TIM16_BASE,
7793
PWM_17 = (int)TIM17_BASE,
78-
PWM_20 = (int)TIM20_BASE
94+
#if defined TIM20_BASE
95+
PWM_20 = (int)TIM20_BASE,
96+
#endif
7997
} PWMName;
8098

8199
typedef enum {
82100
CAN_1 = (int)FDCAN1_BASE,
101+
#if defined FDCAN2_BASE
83102
CAN_2 = (int)FDCAN2_BASE,
84-
CAN_3 = (int)FDCAN3_BASE
103+
#endif
104+
#if defined FDCAN3_BASE
105+
CAN_3 = (int)FDCAN3_BASE,
106+
#endif
85107
} CANName;
86108

109+
#if defined QSPI_R_BASE
87110
typedef enum {
88111
QSPI_1 = (int)QSPI_R_BASE,
89112
} QSPIName;
113+
#endif
90114

91115
typedef enum {
92116
USB_FS = (int)USB_BASE

‎targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/CMSIS/stm32g431xx.h

Lines changed: 32 additions & 45 deletions
Original file line numberDiff line numberDiff line change
@@ -1438,10 +1438,6 @@ typedef struct
14381438
#define ADC_CFGR2_SMPTRIG_Msk (0x1UL << ADC_CFGR2_SMPTRIG_Pos) /*!< 0x08000000 */
14391439
#define ADC_CFGR2_SMPTRIG ADC_CFGR2_SMPTRIG_Msk /*!< ADC Sample Time Control Trigger mode */
14401440

1441-
#define ADC_CFGR2_LFTRIG_Pos (29U)
1442-
#define ADC_CFGR2_LFTRIG_Msk (0x1UL << ADC_CFGR2_LFTRIG_Pos) /*!< 0x20000000 */
1443-
#define ADC_CFGR2_LFTRIG ADC_CFGR2_LFTRIG_Msk /*!< ADC Low Frequency Trigger */
1444-
14451441
/******************** Bit definition for ADC_SMPR1 register *****************/
14461442
#define ADC_SMPR1_SMP0_Pos (0U)
14471443
#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */
@@ -2228,11 +2224,11 @@ typedef struct
22282224

22292225
#define COMP_CSR_BRGEN_Pos (22U)
22302226
#define COMP_CSR_BRGEN_Msk (0x1UL << COMP_CSR_BRGEN_Pos) /*!< 0x00400000 */
2231-
#define COMP_CSR_BRGEN COMP_CSR_BRGEN_Msk /*!< Comparator voltage scaler enable */
2227+
#define COMP_CSR_BRGEN COMP_CSR_BRGEN_Msk /*!< Comparator scaler bridge enable */
22322228

22332229
#define COMP_CSR_SCALEN_Pos (23U)
22342230
#define COMP_CSR_SCALEN_Msk (0x1UL << COMP_CSR_SCALEN_Pos) /*!< 0x00800000 */
2235-
#define COMP_CSR_SCALEN COMP_CSR_SCALEN_Msk /*!< Comparator scaler bridge enable */
2231+
#define COMP_CSR_SCALEN COMP_CSR_SCALEN_Msk /*!< Comparator voltage scaler enable */
22362232

22372233
#define COMP_CSR_VALUE_Pos (30U)
22382234
#define COMP_CSR_VALUE_Msk (0x1UL << COMP_CSR_VALUE_Pos) /*!< 0x40000000 */
@@ -2303,7 +2299,6 @@ typedef struct
23032299
#define CORDIC_RDATA_RES_Msk (0xFFFFFFFFUL << CORDIC_RDATA_RES_Pos) /*!< 0xFFFFFFFF */
23042300
#define CORDIC_RDATA_RES CORDIC_RDATA_RES_Msk /*!< Output Result */
23052301

2306-
23072302
/******************************************************************************/
23082303
/* */
23092304
/* CRC calculation unit */
@@ -2452,9 +2447,9 @@ typedef struct
24522447
/* */
24532448
/******************************************************************************/
24542449
/*
2455-
* @brief Specific device feature definitions (not present on all devices in the STM32G4 serie)
2450+
* @brief Specific device feature definitions (not present on all devices in the STM32G4 series)
24562451
*/
2457-
#define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: DAC channel 2 available */
2452+
#define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: DAC channel 2 available */
24582453

24592454
/******************** Bit definition for DAC_CR register ********************/
24602455
#define DAC_CR_EN1_Pos (0U)
@@ -2658,7 +2653,6 @@ typedef struct
26582653
#define DAC_SR_BWST1_Msk (0x1UL << DAC_SR_BWST1_Pos) /*!< 0x00008000 */
26592654
#define DAC_SR_BWST1 DAC_SR_BWST1_Msk /*!<DAC channel1 busy writing sample time flag */
26602655

2661-
26622656
#define DAC_SR_DAC2RDY_Pos (27U)
26632657
#define DAC_SR_DAC2RDY_Msk (0x1UL << DAC_SR_DAC2RDY_Pos) /*!< 0x08000000 */
26642658
#define DAC_SR_DAC2RDY DAC_SR_DAC2RDY_Msk /*!<DAC channel 2 ready status bit */
@@ -2874,7 +2868,6 @@ typedef struct
28742868
#define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Pos)/*!< 0x80000000 */
28752869
#define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Msk
28762870

2877-
/******************** Bit definition for DBGMCU_APB1FZR2 register **********/
28782871

28792872
/******************** Bit definition for DBGMCU_APB2FZ register ************/
28802873
#define DBGMCU_APB2FZ_DBG_TIM1_STOP_Pos (11U)
@@ -8847,19 +8840,19 @@ typedef struct
88478840
#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk
88488841

88498842
/******************** Bits definition for TAMP_FLTCR register ***************/
8850-
#define TAMP_FLTCR_TAMPFREQ_0 ((uint32_t)0x00000001)
8851-
#define TAMP_FLTCR_TAMPFREQ_1 ((uint32_t)0x00000002)
8852-
#define TAMP_FLTCR_TAMPFREQ_2 ((uint32_t)0x00000004)
8843+
#define TAMP_FLTCR_TAMPFREQ_0 (0x00000001UL)
8844+
#define TAMP_FLTCR_TAMPFREQ_1 (0x00000002UL)
8845+
#define TAMP_FLTCR_TAMPFREQ_2 (0x00000004UL)
88538846
#define TAMP_FLTCR_TAMPFREQ_Pos (0U)
88548847
#define TAMP_FLTCR_TAMPFREQ_Msk (0x7UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000007 */
88558848
#define TAMP_FLTCR_TAMPFREQ TAMP_FLTCR_TAMPFREQ_Msk
8856-
#define TAMP_FLTCR_TAMPFLT_0 ((uint32_t)0x00000008)
8857-
#define TAMP_FLTCR_TAMPFLT_1 ((uint32_t)0x00000010)
8849+
#define TAMP_FLTCR_TAMPFLT_0 (0x00000008UL)
8850+
#define TAMP_FLTCR_TAMPFLT_1 (0x00000010UL)
88588851
#define TAMP_FLTCR_TAMPFLT_Pos (3U)
88598852
#define TAMP_FLTCR_TAMPFLT_Msk (0x3UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000018 */
88608853
#define TAMP_FLTCR_TAMPFLT TAMP_FLTCR_TAMPFLT_Msk
8861-
#define TAMP_FLTCR_TAMPPRCH_0 ((uint32_t)0x00000020)
8862-
#define TAMP_FLTCR_TAMPPRCH_1 ((uint32_t)0x00000040)
8854+
#define TAMP_FLTCR_TAMPPRCH_0 (0x00000020UL)
8855+
#define TAMP_FLTCR_TAMPPRCH_1 (0x00000040UL)
88638856
#define TAMP_FLTCR_TAMPPRCH_Pos (5U)
88648857
#define TAMP_FLTCR_TAMPPRCH_Msk (0x3UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000060 */
88658858
#define TAMP_FLTCR_TAMPPRCH TAMP_FLTCR_TAMPPRCH_Msk
@@ -9903,35 +9896,36 @@ typedef struct
99039896

99049897
/****************** Bit definition for SYSCFG_SWPR register ****************/
99059898
#define SYSCFG_SWPR_PAGE0_Pos (0U)
9906-
#define SYSCFG_SWPR_PAGE0_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE0_Pos) /*!< 0x00000001 */
9907-
#define SYSCFG_SWPR_PAGE0 (uint32_t)(SYSCFG_SWPR_PAGE0_Msk) /*!< CCMSRAM Write protection page 0 */
9899+
#define SYSCFG_SWPR_PAGE0_Msk (0x1UL << SYSCFG_SWPR_PAGE0_Pos) /*!< 0x00000001 */
9900+
#define SYSCFG_SWPR_PAGE0 (SYSCFG_SWPR_PAGE0_Msk) /*!< CCMSRAM Write protection page 0 */
99089901
#define SYSCFG_SWPR_PAGE1_Pos (1U)
9909-
#define SYSCFG_SWPR_PAGE1_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE1_Pos) /*!< 0x00000002 */
9910-
#define SYSCFG_SWPR_PAGE1 (uint32_t)(SYSCFG_SWPR_PAGE1_Msk) /*!< CCMSRAM Write protection page 1 */
9902+
#define SYSCFG_SWPR_PAGE1_Msk (0x1UL << SYSCFG_SWPR_PAGE1_Pos) /*!< 0x00000002 */
9903+
#define SYSCFG_SWPR_PAGE1 (SYSCFG_SWPR_PAGE1_Msk) /*!< CCMSRAM Write protection page 1 */
99119904
#define SYSCFG_SWPR_PAGE2_Pos (2U)
9912-
#define SYSCFG_SWPR_PAGE2_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE2_Pos) /*!< 0x00000004 */
9913-
#define SYSCFG_SWPR_PAGE2 (uint32_t)(SYSCFG_SWPR_PAGE2_Msk) /*!< CCMSRAM Write protection page 2 */
9905+
#define SYSCFG_SWPR_PAGE2_Msk (0x1UL << SYSCFG_SWPR_PAGE2_Pos) /*!< 0x00000004 */
9906+
#define SYSCFG_SWPR_PAGE2 (SYSCFG_SWPR_PAGE2_Msk) /*!< CCMSRAM Write protection page 2 */
99149907
#define SYSCFG_SWPR_PAGE3_Pos (3U)
9915-
#define SYSCFG_SWPR_PAGE3_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE3_Pos) /*!< 0x00000008 */
9916-
#define SYSCFG_SWPR_PAGE3 (uint32_t)(SYSCFG_SWPR_PAGE3_Msk) /*!< CCMSRAM Write protection page 3 */
9908+
#define SYSCFG_SWPR_PAGE3_Msk (0x1UL << SYSCFG_SWPR_PAGE3_Pos) /*!< 0x00000008 */
9909+
#define SYSCFG_SWPR_PAGE3 (SYSCFG_SWPR_PAGE3_Msk) /*!< CCMSRAM Write protection page 3 */
99179910
#define SYSCFG_SWPR_PAGE4_Pos (4U)
9918-
#define SYSCFG_SWPR_PAGE4_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE4_Pos) /*!< 0x00000010 */
9919-
#define SYSCFG_SWPR_PAGE4 (uint32_t)(SYSCFG_SWPR_PAGE4_Msk) /*!< CCMSRAM Write protection page 4 */
9911+
#define SYSCFG_SWPR_PAGE4_Msk (0x1UL << SYSCFG_SWPR_PAGE4_Pos) /*!< 0x00000010 */
9912+
#define SYSCFG_SWPR_PAGE4 (SYSCFG_SWPR_PAGE4_Msk) /*!< CCMSRAM Write protection page 4 */
99209913
#define SYSCFG_SWPR_PAGE5_Pos (5U)
9921-
#define SYSCFG_SWPR_PAGE5_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE5_Pos) /*!< 0x00000020 */
9922-
#define SYSCFG_SWPR_PAGE5 (uint32_t)(SYSCFG_SWPR_PAGE5_Msk) /*!< CCMSRAM Write protection page 5 */
9914+
#define SYSCFG_SWPR_PAGE5_Msk (0x1UL << SYSCFG_SWPR_PAGE5_Pos) /*!< 0x00000020 */
9915+
#define SYSCFG_SWPR_PAGE5 (SYSCFG_SWPR_PAGE5_Msk) /*!< CCMSRAM Write protection page 5 */
99239916
#define SYSCFG_SWPR_PAGE6_Pos (6U)
9924-
#define SYSCFG_SWPR_PAGE6_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE6_Pos) /*!< 0x00000040 */
9925-
#define SYSCFG_SWPR_PAGE6 (uint32_t)(SYSCFG_SWPR_PAGE6_Msk) /*!< CCMSRAM Write protection page 6 */
9917+
#define SYSCFG_SWPR_PAGE6_Msk (0x1UL << SYSCFG_SWPR_PAGE6_Pos) /*!< 0x00000040 */
9918+
#define SYSCFG_SWPR_PAGE6 (SYSCFG_SWPR_PAGE6_Msk) /*!< CCMSRAM Write protection page 6 */
99269919
#define SYSCFG_SWPR_PAGE7_Pos (7U)
9927-
#define SYSCFG_SWPR_PAGE7_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE7_Pos) /*!< 0x00000080 */
9928-
#define SYSCFG_SWPR_PAGE7 (uint32_t)(SYSCFG_SWPR_PAGE7_Msk) /*!< CCMSRAM Write protection page 7 */
9920+
#define SYSCFG_SWPR_PAGE7_Msk (0x1UL << SYSCFG_SWPR_PAGE7_Pos) /*!< 0x00000080 */
9921+
#define SYSCFG_SWPR_PAGE7 (SYSCFG_SWPR_PAGE7_Msk) /*!< CCMSRAM Write protection page 7 */
99299922
#define SYSCFG_SWPR_PAGE8_Pos (8U)
9930-
#define SYSCFG_SWPR_PAGE8_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE8_Pos) /*!< 0x00000100 */
9931-
#define SYSCFG_SWPR_PAGE8 (uint32_t)(SYSCFG_SWPR_PAGE8_Msk) /*!< CCMSRAM Write protection page 8 */
9923+
#define SYSCFG_SWPR_PAGE8_Msk (0x1UL << SYSCFG_SWPR_PAGE8_Pos) /*!< 0x00000100 */
9924+
#define SYSCFG_SWPR_PAGE8 (SYSCFG_SWPR_PAGE8_Msk) /*!< CCMSRAM Write protection page 8 */
99329925
#define SYSCFG_SWPR_PAGE9_Pos (9U)
9933-
#define SYSCFG_SWPR_PAGE9_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE9_Pos) /*!< 0x00000200 */
9934-
#define SYSCFG_SWPR_PAGE9 (uint32_t)(SYSCFG_SWPR_PAGE9_Msk) /*!< CCMSRAM Write protection page 9 */
9926+
#define SYSCFG_SWPR_PAGE9_Msk (0x1UL << SYSCFG_SWPR_PAGE9_Pos) /*!< 0x00000200 */
9927+
#define SYSCFG_SWPR_PAGE9 (SYSCFG_SWPR_PAGE9_Msk) /*!< CCMSRAM Write protection page 9 */
9928+
99359929
/****************** Bit definition for SYSCFG_SKR register ****************/
99369930
#define SYSCFG_SKR_KEY_Pos (0U)
99379931
#define SYSCFG_SKR_KEY_Msk (0xFFUL << SYSCFG_SKR_KEY_Pos) /*!< 0x000000FF */
@@ -12538,7 +12532,6 @@ typedef struct
1253812532
*/
1253912533

1254012534
/******************************* ADC Instances ********************************/
12541-
1254212535
#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
1254312536
((INSTANCE) == ADC2))
1254412537

@@ -12618,7 +12611,6 @@ typedef struct
1261812611
((INSTANCE) == OPAMP2) || \
1261912612
((INSTANCE) == OPAMP3))
1262012613

12621-
1262212614
/******************************** PCD Instances *******************************/
1262312615
#define IS_PCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
1262412616

@@ -12945,7 +12937,6 @@ typedef struct
1294512937
((INSTANCE) == TIM15))
1294612938

1294712939
/****************** TIM Instances : supporting OCxREF clear *******************/
12948-
1294912940
#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
1295012941
((INSTANCE) == TIM2) || \
1295112942
((INSTANCE) == TIM3) || \
@@ -12978,9 +12969,6 @@ typedef struct
1297812969
((INSTANCE) == TIM16) || \
1297912970
((INSTANCE) == TIM17))
1298012971

12981-
/****************** TIM Instances : supporting synchronization ****************/
12982-
#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)
12983-
1298412972
/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
1298512973
#define IS_TIM_TRGO2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
1298612974
((INSTANCE) == TIM8))
@@ -13003,7 +12991,6 @@ typedef struct
1300312991
((INSTANCE) == TIM16) || \
1300412992
((INSTANCE) == TIM17))
1300512993

13006-
1300712994
/****************** TIM Instances : Advanced timer instances *******************/
1300812995
#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
1300912996
((INSTANCE) == TIM8))

0 commit comments

Comments
 (0)