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Arto Kinnunen
committed
Sync with STM S2LP RF driver v0.0.1
Sync with v0.0.1 in master repository.
1 parent 2c78427 commit e8225fb

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4 files changed

+132
-40
lines changed

4 files changed

+132
-40
lines changed

components/802.15.4_RF/stm-s2lp-rf-driver/source/NanostackRfPhys2lp.cpp

Lines changed: 102 additions & 38 deletions
Original file line numberDiff line numberDiff line change
@@ -206,15 +206,24 @@ static uint16_t tx_sequence = 0xffff;
206206
static uint32_t tx_time = 0;
207207
static uint32_t rx_time = 0;
208208
static uint32_t tx_finnish_time = 0;
209-
static uint32_t symbols_in_seconds;
209+
static uint32_t rf_symbol_rate;
210210
static bool cca_enabled = true;
211211
static uint8_t s2lp_PAN_ID[2] = {0xff, 0xff};
212212
static uint8_t s2lp_short_address[2];
213213
static uint8_t s2lp_MAC[8];
214214
static rf_mode_e rf_mode = RF_MODE_NORMAL;
215+
static bool rf_update_config = false;
215216

216217
/* Channel configurations for sub-GHz */
217-
static const phy_rf_channel_configuration_s phy_subghz = {868300000U, 500000U, 250000U, 11U, M_UNDEFINED};
218+
static phy_rf_channel_configuration_s phy_subghz = {
219+
.channel_0_center_frequency = 868300000U,
220+
.channel_spacing = 500000U,
221+
.datarate = 250000U,
222+
.number_of_channels = 11U,
223+
.modulation = M_2FSK,
224+
.modulation_index = MODULATION_INDEX_UNDEFINED
225+
};
226+
218227

219228
static const phy_device_channel_page_s phy_channel_pages[] = {
220229
{ CHANNEL_PAGE_2, &phy_subghz},
@@ -236,8 +245,8 @@ static void rf_irq_task_process_irq();
236245

237246
#define ACK_FRAME_LENGTH 3
238247
// Give some additional time for processing, PHY headers, CRC etc.
239-
#define PACKET_SENDING_EXTRA_TIME 10000
240-
#define MAX_PACKET_SENDING_TIME (uint32_t)(8000000/phy_subghz.datarate)*RF_MTU + PACKET_SENDING_EXTRA_TIME
248+
#define PACKET_SENDING_EXTRA_TIME 5000
249+
#define MAX_PACKET_SENDING_TIME (uint32_t)(8000000/phy_subghz.datarate)*FIFO_SIZE + PACKET_SENDING_EXTRA_TIME
241250
#define ACK_SENDING_TIME (uint32_t)(8000000/phy_subghz.datarate)*ACK_FRAME_LENGTH + PACKET_SENDING_EXTRA_TIME
242251

243252
#ifdef TEST_GPIOS_ENABLED
@@ -259,11 +268,11 @@ void test2_toggle(void)
259268
}
260269
#endif //TEST_GPIOS_ENABLED
261270

262-
static void rf_calculate_symbols_in_seconds(uint32_t baudrate, phy_modulation_e modulation)
271+
static void rf_calculate_symbol_rate(uint32_t baudrate, phy_modulation_e modulation)
263272
{
264273
(void) modulation;
265274
uint8_t bits_in_symbols = 1;
266-
symbols_in_seconds = baudrate / bits_in_symbols;
275+
rf_symbol_rate = baudrate / bits_in_symbols;
267276
}
268277

269278
static uint32_t rf_get_timestamp(void)
@@ -419,12 +428,13 @@ static void rf_state_change(s2lp_states_e state, bool lock_mode_tx)
419428
rf_poll_state_change(state);
420429
}
421430

422-
static uint8_t rf_write_tx_fifo(uint8_t *ptr, uint16_t length, uint8_t max_write)
431+
static uint8_t rf_write_tx_fifo(uint8_t *ptr, uint16_t length)
423432
{
433+
uint8_t free_bytes_in_fifo = FIFO_SIZE - rf_read_register(TX_FIFO_STATUS);
424434
const uint8_t spi_header[SPI_HEADER_LENGTH] = {SPI_WR_REG, TX_FIFO};
425435
uint8_t written_length = length;
426-
if (length > max_write) {
427-
written_length = max_write;
436+
if (length > free_bytes_in_fifo) {
437+
written_length = free_bytes_in_fifo;
428438
}
429439
CS_SELECT();
430440
rf_spi_exchange(spi_header, SPI_HEADER_LENGTH, NULL, 0);
@@ -463,28 +473,30 @@ static uint32_t read_irq_status(void)
463473
return (((uint32_t)rx[2] << 24) | ((uint32_t)rx[3] << 16) | ((uint32_t)rx[4] << 8) | rx[5]);
464474
}
465475

466-
static void rf_init_registers(void)
476+
static void rf_set_channel_configuration_registers(void)
467477
{
468-
rf_write_register_field(PCKTCTRL3, PCKT_FORMAT_FIELD, PCKT_FORMAT_802_15_4);
469478
// Set deviation
479+
uint32_t deviation = rf_conf_calculate_deviation(phy_subghz.modulation_index, phy_subghz.datarate);
480+
if (!deviation) {
481+
deviation = DEFAULT_DEVIATION;
482+
}
470483
uint8_t fdev_m, fdev_e;
471-
rf_conf_calculate_deviation_registers(DEVIATION, &fdev_m, &fdev_e);
484+
rf_conf_calculate_deviation_registers(deviation, &fdev_m, &fdev_e);
472485
rf_write_register(MOD0, fdev_m);
473486
rf_write_register_field(MOD1, FDEV_E_FIELD, fdev_e);
474-
rf_write_register_field(MOD2, MOD_TYPE_FIELD, MOD_2FSK);
487+
475488
// Set datarate
476489
uint16_t datarate_m;
477490
uint8_t datarate_e;
478491
rf_conf_calculate_datarate_registers(phy_subghz.datarate, &datarate_m, &datarate_e);
479492
rf_write_register_field(MOD2, DATARATE_E_FIELD, datarate_e);
480493
rf_write_register(MOD3, (uint8_t)datarate_m);
481494
rf_write_register(MOD4, datarate_m >> 8);
482-
// Set RX filter bandwidth
495+
// Set RX filter bandwidth, using channel spacing as RX filter bandwidth
483496
uint8_t chflt_m, chflt_e;
484-
rf_conf_calculate_rx_filter_bandwidth_registers(RX_FILTER_BANDWIDTH, &chflt_m, &chflt_e);
497+
rf_conf_calculate_rx_filter_bandwidth_registers(phy_subghz.channel_spacing, &chflt_m, &chflt_e);
485498
rf_write_register_field(CHFLT, CHFLT_M_FIELD, chflt_m << 4);
486499
rf_write_register_field(CHFLT, CHFLT_E_FIELD, chflt_e);
487-
rf_write_register(PCKT_FLT_OPTIONS, 0);
488500
// Set base frequency (Channel 0 center frequency)
489501
uint8_t synt3, synt2, synt1, synt0;
490502
rf_conf_calculate_base_frequency_registers(phy_subghz.channel_0_center_frequency, &synt3, &synt2, &synt1, &synt0);
@@ -500,6 +512,19 @@ static void rf_init_registers(void)
500512
rf_channel_multiplier++;
501513
}
502514
rf_write_register(CHSPACE, ch_space);
515+
tr_info("RF config update:");
516+
tr_info("Frequency(ch0): %luHz", phy_subghz.channel_0_center_frequency);
517+
tr_info("Channel spacing: %luHz", phy_subghz.channel_spacing);
518+
tr_info("Datarate: %lubps", phy_subghz.datarate);
519+
tr_info("Deviation: %luHz", deviation);
520+
tr_info("RX BW M: %u, E: %u", chflt_m, chflt_e);
521+
}
522+
523+
static void rf_init_registers(void)
524+
{
525+
rf_write_register_field(PCKTCTRL3, PCKT_FORMAT_FIELD, PCKT_FORMAT_802_15_4);
526+
rf_write_register_field(MOD2, MOD_TYPE_FIELD, MOD_2FSK);
527+
rf_write_register(PCKT_FLT_OPTIONS, 0);
503528
rf_write_register_field(PCKTCTRL1, PCKT_CRCMODE_FIELD, PCKT_CRCMODE_0X1021);
504529
rf_write_register_field(PCKTCTRL1, PCKT_TXSOURCE_FIELD, PCKT_TXSOURCE_NORMAL);
505530
rf_write_register_field(PCKTCTRL1, PCKT_WHITENING_FIELD, PCKT_WHITENING_ENABLED);
@@ -515,6 +540,7 @@ static void rf_init_registers(void)
515540
uint8_t rssi_th;
516541
rf_conf_calculate_rssi_threshold_registers(RSSI_THRESHOLD, &rssi_th);
517542
rf_write_register(RSSI_TH, rssi_th);
543+
rf_set_channel_configuration_registers();
518544
}
519545

520546
static int8_t rf_address_write(phy_address_type_e address_type, uint8_t *address_ptr)
@@ -544,6 +570,7 @@ static int8_t rf_extension(phy_extension_type_e extension_type, uint8_t *data_pt
544570
{
545571
int8_t retval = 0;
546572
phy_csma_params_t *csma_params;
573+
phy_rf_channel_configuration_s *channel_params;
547574
uint32_t *timer_value;
548575
switch (extension_type) {
549576
case PHY_EXTENSION_SET_CHANNEL:
@@ -602,9 +629,22 @@ static int8_t rf_extension(phy_extension_type_e extension_type, uint8_t *data_pt
602629

603630
case PHY_EXTENSION_GET_SYMBOLS_PER_SECOND:
604631
timer_value = (uint32_t *)data_ptr;
605-
*timer_value = symbols_in_seconds;
632+
*timer_value = rf_symbol_rate;
633+
break;
634+
case PHY_EXTENSION_SET_RF_CONFIGURATION:
635+
channel_params = (phy_rf_channel_configuration_s *)data_ptr;
636+
phy_subghz.datarate = channel_params->datarate;
637+
phy_subghz.channel_spacing = channel_params->channel_spacing;
638+
phy_subghz.channel_0_center_frequency = channel_params->channel_0_center_frequency;
639+
phy_subghz.number_of_channels = channel_params->number_of_channels;
640+
phy_subghz.modulation = channel_params->modulation;
641+
phy_subghz.modulation_index = channel_params->modulation_index;
642+
rf_calculate_symbol_rate(phy_subghz.datarate, phy_subghz.modulation);
643+
rf_update_config = true;
644+
if (rf_state == RF_IDLE) {
645+
rf_receive(rf_rx_channel);
646+
}
606647
break;
607-
608648
default:
609649
break;
610650
}
@@ -660,28 +700,30 @@ static void rf_tx_sent_handler(void)
660700

661701
static void rf_tx_threshold_handler(void)
662702
{
703+
rf_backup_timer_stop();
663704
rf_disable_interrupt(TX_FIFO_ALMOST_EMPTY);
664705
// TODO check the FIFO threshold. By default, threshold is half of the FIFO size
665-
uint8_t written_length = rf_write_tx_fifo(tx_data_ptr, tx_data_length, FIFO_SIZE / 2);
706+
uint8_t written_length = rf_write_tx_fifo(tx_data_ptr, tx_data_length);
666707
if (written_length < tx_data_length) {
667708
tx_data_ptr += written_length;
668709
tx_data_length -= written_length;
669710
rf_enable_interrupt(TX_FIFO_ALMOST_EMPTY);
670711
}
712+
rf_backup_timer_start(MAX_PACKET_SENDING_TIME);
671713
}
672714

673715
static void rf_start_tx(void)
674716
{
717+
rf_send_command(S2LP_CMD_SABORT);
675718
rf_disable_all_interrupts();
719+
rf_poll_state_change(S2LP_STATE_READY);
720+
rf_state_change(S2LP_STATE_TX, false);
676721
// More TX data to be written in FIFO when TX threshold interrupt occurs
677722
if (tx_data_ptr) {
678723
rf_enable_interrupt(TX_FIFO_ALMOST_EMPTY);
679724
}
680725
rf_enable_interrupt(TX_DATA_SENT);
681726
rf_enable_interrupt(TX_FIFO_UNF_OVF);
682-
rf_state_change(S2LP_STATE_READY, false);
683-
rf_state_change(S2LP_STATE_LOCK, true);
684-
rf_state_change(S2LP_STATE_TX, false);
685727
rf_backup_timer_start(MAX_PACKET_SENDING_TIME);
686728
}
687729

@@ -694,7 +736,7 @@ static void rf_cca_timer_interrupt(void)
694736
rf_state = RF_IDLE;
695737
return;
696738
}
697-
if ((cca_enabled == true) && (rf_read_register(LINK_QUALIF1) & CARRIER_SENSE || (rf_state != RF_CSMA_STARTED && rf_state != RF_IDLE))) {
739+
if ((cca_enabled == true) && ((rf_state != RF_CSMA_STARTED && rf_state != RF_IDLE) || (read_irq_status() & (1 << SYNC_WORD)) || (rf_read_register(LINK_QUALIF1) & CARRIER_SENSE))) {
698740
if (rf_state == RF_CSMA_STARTED) {
699741
rf_state = RF_IDLE;
700742
}
@@ -765,7 +807,7 @@ static int8_t rf_start_cca(uint8_t *data_ptr, uint16_t data_length, uint8_t tx_h
765807
return -1;
766808
}
767809
rf_state = RF_CSMA_STARTED;
768-
uint8_t written_length = rf_write_tx_fifo(data_ptr, data_length, FIFO_SIZE);
810+
uint8_t written_length = rf_write_tx_fifo(data_ptr, data_length);
769811
if (written_length < data_length) {
770812
tx_data_ptr = data_ptr + written_length;
771813
tx_data_length = data_length - written_length;
@@ -789,7 +831,8 @@ static int8_t rf_start_cca(uint8_t *data_ptr, uint16_t data_length, uint8_t tx_h
789831
return 0;
790832
}
791833
}
792-
rf_cca_timer_interrupt();
834+
// Short timeout to start CCA immediately.
835+
rf_cca_timer_start(1);
793836
rf_unlock();
794837
return 0;
795838
}
@@ -805,7 +848,7 @@ static void rf_send_ack(uint8_t seq)
805848
}
806849
rf_state = RF_TX_ACK;
807850
uint8_t ack_frame[3] = {MAC_TYPE_ACK, 0, seq};
808-
rf_write_tx_fifo(ack_frame, sizeof(ack_frame), FIFO_SIZE);
851+
rf_write_tx_fifo(ack_frame, sizeof(ack_frame));
809852
rf_write_packet_length(sizeof(ack_frame) + 4);
810853
tx_data_ptr = NULL;
811854
rf_start_tx();
@@ -841,11 +884,11 @@ static void rf_rx_ready_handler(void)
841884
}
842885
rx_data_length += rx_read_length;
843886
if (rf_mode != RF_MODE_SNIFFER) {
887+
rf_state = RF_IDLE;
844888
uint8_t version = ((rx_buffer[1] & VERSION_FIELD_MASK) >> SHIFT_VERSION_FIELD);
845889
if (((rx_buffer[0] & MAC_FRAME_TYPE_MASK) == MAC_TYPE_ACK) && (version < MAC_FRAME_VERSION_2)) {
846890
rf_handle_ack(rx_buffer[2], rx_buffer[0] & MAC_DATA_PENDING);
847891
} else if (rf_rx_filter(rx_buffer, s2lp_MAC, s2lp_short_address, s2lp_PAN_ID)) {
848-
rf_state = RF_IDLE;
849892
int8_t rssi = (rf_read_register(RSSI_LEVEL) - RSSI_OFFSET);
850893
if (device_driver.phy_rx_cb) {
851894
device_driver.phy_rx_cb(rx_buffer, rx_data_length, 0xf0, rssi, rf_radio_driver_id);
@@ -869,12 +912,14 @@ static void rf_rx_ready_handler(void)
869912

870913
static void rf_rx_threshold_handler(void)
871914
{
915+
rf_backup_timer_stop();
872916
int rx_read_length = rf_read_rx_fifo(rx_data_length, rf_read_register(RX_FIFO_STATUS));
873917
if (rx_read_length < 0) {
874918
rf_receive(rf_rx_channel);
875919
return;
876920
}
877921
rx_data_length += rx_read_length;
922+
rf_backup_timer_start(MAX_PACKET_SENDING_TIME);
878923
}
879924

880925
static void rf_sync_detected_handler(void)
@@ -896,6 +941,10 @@ static void rf_receive(uint8_t rx_channel)
896941
rf_state_change(S2LP_STATE_READY, false);
897942
rf_send_command(S2LP_CMD_FLUSHRXFIFO);
898943
rf_poll_state_change(S2LP_STATE_READY);
944+
if (rf_update_config == true) {
945+
rf_update_config = false;
946+
rf_set_channel_configuration_registers();
947+
}
899948
if (rx_channel != rf_rx_channel) {
900949
rf_write_register(CHNUM, rx_channel * rf_channel_multiplier);
901950
rf_rx_channel = rf_new_channel = rx_channel;
@@ -953,17 +1002,18 @@ static void rf_interrupt_handler(void)
9531002
}
9541003
}
9551004
if ((irq_status & (1 << TX_FIFO_UNF_OVF)) && (enabled_interrupts & (1 << TX_FIFO_UNF_OVF))) {
1005+
rf_backup_timer_stop();
9561006
tx_finnish_time = rf_get_timestamp();
9571007
TEST_TX_DONE
958-
device_driver.phy_tx_done_cb(rf_radio_driver_id, mac_tx_handle, PHY_LINK_TX_FAIL, 1, 0);
1008+
device_driver.phy_tx_done_cb(rf_radio_driver_id, mac_tx_handle, PHY_LINK_CCA_FAIL, 1, 0);
9591009
rf_send_command(S2LP_CMD_SABORT);
9601010
rf_poll_state_change(S2LP_STATE_READY);
9611011
rf_send_command(S2LP_CMD_FLUSHTXFIFO);
9621012
rf_poll_state_change(S2LP_STATE_READY);
9631013
rf_state = RF_IDLE;
9641014
rf_receive(rf_rx_channel);
9651015
}
966-
if (rf_state == RF_IDLE || rf_state == RF_TX_STARTED) {
1016+
if (rf_state == RF_IDLE || rf_state == RF_CSMA_STARTED || rf_state == RF_TX_STARTED) {
9671017
if ((irq_status & (1 << SYNC_WORD)) && (enabled_interrupts & (1 << SYNC_WORD))) {
9681018
rf_sync_detected_handler();
9691019
}
@@ -972,6 +1022,8 @@ static void rf_interrupt_handler(void)
9721022
if (!(irq_status & (1 << CRC_ERROR))) {
9731023
rf_rx_ready_handler();
9741024
} else {
1025+
TEST_RX_DONE
1026+
rf_backup_timer_stop();
9751027
rf_state = RF_IDLE;
9761028
// In case the channel change was called during reception, driver is responsible to change the channel if CRC failed.
9771029
rf_receive(rf_new_channel);
@@ -1006,8 +1058,7 @@ static void rf_reset(void)
10061058
wait_ms(10);
10071059
// Wake up
10081060
rf->SDN = 0;
1009-
// Wait until GPIO0 (RESETN) goes high
1010-
while (rf->RF_S2LP_GPIO0 == 0);
1061+
wait_ms(10);
10111062
}
10121063

10131064
static void rf_init(void)
@@ -1019,15 +1070,9 @@ static void rf_init(void)
10191070
rf_reset();
10201071
rf->spi.frequency(10000000);
10211072
CS_RELEASE();
1022-
if (PARTNUM != rf_read_register(DEVICE_INFO1)) {
1023-
tr_err("Invalid part number: %x", rf_read_register(DEVICE_INFO1));
1024-
}
1025-
if (VERSION != rf_read_register(DEVICE_INFO0)) {
1026-
tr_err("Invalid version: %x", rf_read_register(DEVICE_INFO0));
1027-
}
10281073
rf_init_registers();
10291074
rf_enable_gpio_interrupt();
1030-
rf_calculate_symbols_in_seconds(phy_subghz.datarate, phy_subghz.modulation);
1075+
rf_calculate_symbol_rate(phy_subghz.datarate, phy_subghz.modulation);
10311076
rf->tx_timer.start();
10321077
rf_print_registers();
10331078
}
@@ -1071,12 +1116,31 @@ static void rf_device_unregister()
10711116

10721117
void NanostackRfPhys2lp::get_mac_address(uint8_t *mac)
10731118
{
1119+
rf_lock();
1120+
1121+
if (NULL == rf) {
1122+
error("NanostackRfPhys2lp Must be registered to read mac address");
1123+
rf_unlock();
1124+
return;
1125+
}
1126+
memcpy((void*)mac, (void*)_mac_addr, sizeof(_mac_addr));
10741127

1128+
rf_unlock();
10751129
}
10761130

10771131
void NanostackRfPhys2lp::set_mac_address(uint8_t *mac)
10781132
{
1133+
rf_lock();
10791134

1135+
if (NULL != rf) {
1136+
error("NanostackRfPhys2lp cannot change mac address when running");
1137+
rf_unlock();
1138+
return;
1139+
}
1140+
memcpy((void*)_mac_addr, (void*)mac, sizeof(_mac_addr));
1141+
_mac_set = true;
1142+
1143+
rf_unlock();
10801144
}
10811145

10821146
int8_t NanostackRfPhys2lp::rf_register()

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