[NUCLEO_F103RB] 16-bit timer register update

This path fixes issue #816.

Current value of TIM_MST->CNT is read in interrupt context only.
This avoids master timer overflow without SlaveCounter update.

Change-Id: Ie7a9bfce76990f85caa84264450d053604af33e5

Author: kulaaraf

hal/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/hal_tick.c

@@ -43,9 +43,10 @@ void set_compare(uint16_t count);
 extern volatile uint32_t SlaveCounter;
 extern volatile uint32_t oc_int_part;
 extern volatile uint16_t oc_rem_part;
+extern volatile uint16_t cnt_val;
 
 void timer_irq_handler(void) {
-    uint16_t cval = TIM_MST->CNT;
+    cnt_val= TIM_MST->CNT;
 
     TimMasterHandle.Instance = TIM_MST;
 
@@ -64,7 +65,7 @@ void timer_irq_handler(void) {
         } else {
             if (oc_int_part > 0) {
                 set_compare(0xFFFF);
-                oc_rem_part = cval; // To finish the counter loop the next time
+                oc_rem_part = cnt_val; // To finish the counter loop the next time
                 oc_int_part--;
             } else {
                 us_ticker_irq_handler();