User trim added.

radhika-raghavendran · radhika-raghavendran · commit eaf7265aa66f · 2016-10-28T15:02:52.000+05:30
Astyle and pylint run on code.
diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/clock_map.h b/targets/TARGET_ONSEMI/TARGET_NCS36510/clock_map.h
@@ -116,8 +116,27 @@ typedef struct {
     __IO uint32_t WDIV;                                     /**< 0x4001B020 Watchdog clock divider */
     __IO uint32_t TRIM_32M_INT;                             /**< 0x4001B024 32Mhz internal trim */
     __IO uint32_t TRIM_32K_INT;                             /**< 0x4001B02C 32kHz internal trim */
-    __IO uint32_t TRIM_32M_EXT;                             /**< 0x4001B030 32Mhz external trim */
-    __IO uint32_t TRIM_32K_EXT;                             /**< 0x4001B034 32Khz external trim */
+    union {
+        struct {
+            __IO uint32_t TRIM_VALUE :6;    /* External 32MHz Trim Value   */
+            __IO uint32_t BOOST :2;         /* Boost done signal tap control   */
+            __IO uint32_t READY :2;         /* Ready signal tap control   */
+            __IO uint32_t GAIN_MODE :2;     /* Gain Mode   */
+            __IO uint32_t PAD :20;          /* Unused bits   */
+        } BITS;
+        __IO uint32_t WORD;
+    } TRIM_32M_EXT;                                                                 /**< 0x4001B030 32Mhz external trim */
+
+    union {
+        struct {
+            __IO uint32_t TRIM_VALUE :6;    /* External 32MHz Trim Value   */
+            __IO uint32_t BOOST :2;         /* Boost done signal tap control   */
+            __IO uint32_t READY :2;         /* Ready signal tap control   */
+            __IO uint32_t GAIN_MODE :2;     /* Gain Mode   */
+            __IO uint32_t PAD :20;          /* Unused bits   */
+        } BITS;
+        __IO uint32_t WORD;
+    } TRIM_32K_EXT;
     union {
         struct {
             __IO uint32_t OV32M;
diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/memory_map.h b/targets/TARGET_ONSEMI/TARGET_NCS36510/memory_map.h
@@ -109,6 +109,12 @@
 #define TRIMREG_BASE        ((uint32_t)0x1FA0)
 #define TRIMREG             ((TrimReg_t *)TRIMREG_BASE)
 
+/** User trim structure mapping
+ *
+ */
+#define USRETRIMREG_BASE     ((uint32_t)0x2800)
+#define USERTRIMREG          ((UserTrimReg_t *)USRETRIMREG_BASE)
+
 /** DMA HW Registers Offset */
 #define DMAREG_BASE         ((uint32_t)0x24000400)
 /** DMA HW Structure Overlay */
diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/ncs36510Init.c b/targets/TARGET_ONSEMI/TARGET_NCS36510/ncs36510Init.c
@@ -37,6 +37,7 @@
 #include "ncs36510Init.h"
 
 void fPmuInit(void);
+uint32_t ADC_Trim_Offset;
 /**
  * @brief
  * Hardware trimming function
@@ -45,24 +46,35 @@ void fPmuInit(void);
  */
 boolean fTrim()
 {
+    boolean status = False;
 
     /**- Check if trim values are present */
     /**- If Trim data is present.  Only trim if valid trim values are present. */
     /**- Copy trims in registers */
     if (TRIMREG->REVISION_CODE != 0xFFFFFFFF) {
 
+        if ( TRIMREG->MAC_ADDR_LOW != 0xFFFFFFFF ) {
+            MACHWREG->LONG_ADDRESS_LOW = TRIMREG->MAC_ADDR_LOW;
+        }
+
+        if ( TRIMREG->MAC_ADDR_HIGH != 0xFFFFFFFF ) {
+            MACHWREG->LONG_ADDRESS_HIGH = TRIMREG->MAC_ADDR_HIGH;
+        }
+
         /**- board specific clock trims may only be done when present, writing all 1's is not good */
         if ((TRIMREG->TRIM_32K_EXT & 0xFFFF0000) != 0xFFFF0000) {
-            CLOCKREG->TRIM_32K_EXT = TRIMREG->TRIM_32K_EXT;
+            CLOCKREG->TRIM_32K_EXT.WORD = TRIMREG->TRIM_32K_EXT;
         }
 
         if ((TRIMREG->TRIM_32M_EXT & 0xFFFF0000) != 0xFFFF0000) {
-            CLOCKREG->TRIM_32M_EXT = TRIMREG->TRIM_32M_EXT;
+            CLOCKREG->TRIM_32M_EXT.WORD = TRIMREG->TRIM_32M_EXT;
         }
 
         MACHWREG->TX_LENGTH.BITS.TX_PRE_CHIPS = TRIMREG->TX_PRE_CHIPS;
 
-        RFANATRIMREG->TX_CHAIN_TRIM = TRIMREG->TX_CHAIN_TRIM;
+        if ((TRIMREG->TX_TRIM & 0xFFFF0000) != 0xFFFF0000) {
+            RFANATRIMREG->TX_TRIM.WORD = TRIMREG->TX_TRIM;
+        }
         RFANATRIMREG->PLL_VCO_TAP_LOCATION = TRIMREG->PLL_VCO_TAP_LOCATION;
         RFANATRIMREG->PLL_TRIM.WORD = TRIMREG->PLL_TRIM;
 
@@ -75,27 +87,48 @@ boolean fTrim()
         RFANATRIMREG->PMU_TRIM = TRIMREG->PMU_TRIM;
         RANDREG->WR_SEED_RD_RAND = TRIMREG->WR_SEED_RD_RAND;
 
-        /** REVD boards are trimmed (in flash) with rx vco trims specific for high side injection,
-        * */
+        /* High side injection settings */
         RFANATRIMREG->RX_VCO_TRIM_LUT1 = TRIMREG->RX_VCO_LUT1.WORD;;
         RFANATRIMREG->RX_VCO_TRIM_LUT2 = TRIMREG->RX_VCO_LUT2.WORD;;
 
         RFANATRIMREG->TX_VCO_TRIM_LUT1 = TRIMREG->TX_VCO_LUT1.WORD;;
         RFANATRIMREG->TX_VCO_TRIM_LUT2 = TRIMREG->TX_VCO_LUT2.WORD;;
 
-        if ( TRIMREG->MAC_ADDR_LOW != 0xFFFFFFFF ) {
-            MACHWREG->LONG_ADDRESS_LOW = TRIMREG->MAC_ADDR_LOW;
-        }
+        ADC_Trim_Offset = TRIMREG->ADC_OFFSET_TRIM;
 
-        if ( TRIMREG->MAC_ADDR_HIGH != 0xFFFFFFFF ) {
-            MACHWREG->LONG_ADDRESS_HIGH = TRIMREG->MAC_ADDR_HIGH;
-        }
+        status = True;
 
-        return True;
     } else {
-        /**- If no trim values are present, update the global status variable. */
-        return False;
+
+        return(False);
+    }
+
+    /** Read in user trim values programmed in the flash memory
+    The user trim values take precedence over factory trim for MAC address
+    */
+    if (( USERTRIMREG->MAC_ADDRESS_LOW != 0xFFFFFFFF ) &&
+            (USERTRIMREG->MAC_ADDRESS_HIGH != 0xFFFFFFFF)) {
+
+        MACHWREG->LONG_ADDRESS_LOW = USERTRIMREG->MAC_ADDRESS_LOW;
+        MACHWREG->LONG_ADDRESS_HIGH = USERTRIMREG->MAC_ADDRESS_HIGH;
+    }
+
+    if (USERTRIMREG->TRIM_32K_EXT != 0xFFFFFFFF) {
+        CLOCKREG->TRIM_32K_EXT.WORD = (USERTRIMREG->TRIM_32K_EXT & 0x00000FFF);
+    }
+
+    if (USERTRIMREG->TRIM_32K_EXT != 0xFFFFFFFF) {
+        CLOCKREG->TRIM_32K_EXT.WORD = (USERTRIMREG->TRIM_32K_EXT & 0x00000FFF);
+    }
+
+    if (USERTRIMREG->RSSI_OFFSET != 0xFFFFFFFF) {
+        DMDREG->DMD_CONTROL2.BITS.RSSI_OFFSET = (USERTRIMREG->RSSI_OFFSET & 0x0000003F);
+    }
+
+    if (USERTRIMREG->TX_TRIM != 0xFFFFFFFF) {
+        RFANATRIMREG->TX_TRIM.BITS.TX_TUNE = (USERTRIMREG->TX_TRIM & 0x0000000F);
     }
+    return(status);
 }
 
 /* See clock.h for documentation. */
diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/ncs36510_user_trim.json b/targets/TARGET_ONSEMI/TARGET_NCS36510/ncs36510_user_trim.json
@@ -0,0 +1,8 @@
+{
+  "mac-addr-low": "0x12345678",
+  "mac-addr-high": "0xACDE48EF",
+  "32KHz-clk-trim": "0x3A",
+  "32MHz-clk-trim": "0x16",
+  "rssi-trim": "0x3D",
+  "txtune-trim": "0x12"
+}
diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/rfAna_map.h b/targets/TARGET_ONSEMI/TARGET_NCS36510/rfAna_map.h
@@ -104,7 +104,16 @@ typedef struct {
         __IO uint32_t WORD;
     } PLL_TRIM;
     __IO uint32_t PLL_VCO_TAP_LOCATION;
-    __IO uint32_t TX_CHAIN_TRIM;
+    union {
+        struct {
+            __IO uint32_t TX_TUNE:4;
+            __IO uint32_t PA_REGULATOR_TRIM:4;
+            __IO uint32_t REGULATOR_TRIM:2;
+            __IO uint32_t RESERVED:2;
+        } BITS;
+        __IO uint32_t WORD;
+    } TX_TRIM;
+
     __IO uint32_t RX_VCO_TRIM_LUT2;             /** 0x40019098 */
     __IO uint32_t RX_VCO_TRIM_LUT1;             /** 0x4001909C */
     __IO uint32_t TX_VCO_TRIM_LUT2;             /** 0x400190A0 */
diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/sleep.c b/targets/TARGET_ONSEMI/TARGET_NCS36510/sleep.c
@@ -101,10 +101,10 @@ void fncs36510_coma(void)
 
     /** Trim the oscillators */
     if ((TRIMREG->TRIM_32K_EXT & 0xFFFF0000) != 0xFFFF0000) {
-        CLOCKREG->TRIM_32K_EXT = TRIMREG->TRIM_32K_EXT;
+        CLOCKREG->TRIM_32K_EXT.WORD = TRIMREG->TRIM_32K_EXT;
     }
     if ((TRIMREG->TRIM_32M_EXT & 0xFFFF0000) != 0xFFFF0000) {
-        CLOCKREG->TRIM_32M_EXT = TRIMREG->TRIM_32M_EXT;
+        CLOCKREG->TRIM_32M_EXT.WORD = TRIMREG->TRIM_32M_EXT;
     }
 
     /* Enable UART 1 & 2 FIFO */
diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/swversion.c b/targets/TARGET_ONSEMI/TARGET_NCS36510/swversion.c
@@ -42,8 +42,8 @@
  * such that flash loader knows where to find it and gets the build dependent data
  * it needs for programming the new fib.
  */
-__root const fibtable_t fib_table @ "FIBTABLE" = { LOAD_ADDRESS,{0x0,0x00,0x00,0x00}};
-#endif /* IAR */
+__root const fibtable_t fib_table @ "FIBTABLE" = {LOAD_ADDRESS,{0x0,0x00,0x00,0x00}};
+#endif /* __ICCARM__ */
 
 const mib_systemRevision_t systemRevision = {
     0x82,    /**< hardware revision */
diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/trim_map.h b/targets/TARGET_ONSEMI/TARGET_NCS36510/trim_map.h
@@ -113,7 +113,7 @@ typedef struct {
     __I uint32_t ON_RESERVED1;            /**< 0x1FCC */
     __I uint32_t ADC_OFFSET_TRIM;         /**< 0x1FD0 */
     __I uint32_t TX_PRE_CHIPS;            /**< 0x1FD4 */
-    __I uint32_t TX_CHAIN_TRIM;           /**< 0x1FD8 */
+    __I uint32_t TX_TRIM;                 /**< 0x1FD8 */
     __I uint32_t PLL_VCO_TAP_LOCATION;    /**< 0x1FDC */
     __I uint32_t PLL_TRIM;                /**< 0x1FE0 */
     __I uint32_t RSSI_OFFSET;             /**< 0x1FE4 */
@@ -125,4 +125,14 @@ typedef struct {
     __I uint32_t REVISION_CODE;           /**< 0x1FFC */
 } TrimReg_t, *TrimReg_pt;
 
+
+/** User defined trim register map */
+typedef struct {
+    __IO uint32_t MAC_ADDRESS_LOW;		/**< 0x2800     */
+    __IO uint32_t MAC_ADDRESS_HIGH;		/**< 0x2804     */
+    __IO uint32_t TRIM_32K_EXT;		        /**< 0x2808	*/
+    __IO uint32_t TRIM_32M_EXT;		        /**< 0x280C	*/
+    __IO uint32_t RSSI_OFFSET;		        /**< 0x2810	*/
+    __IO uint32_t TX_TRIM;		        /**< 0x2814	*/
+} UserTrimReg_t, *UserTrimReg_pt;
 #endif /* TRIM_MAP_H_ */
diff --git a/tools/add_fib.py b/tools/add_fib.py
@@ -15,10 +15,14 @@
 import itertools
 import binascii
 import intelhex
+import json
+
 
 FIB_BASE = 0x2000
 FLASH_BASE = 0x3000
 FW_REV = 0x01000100
+TRIM_BASE = 0x2800
+
 def ranges(i):
     for _, b in itertools.groupby(enumerate(i), lambda x_y: x_y[1] - x_y[0]):
         b = list(b)
@@ -51,7 +55,7 @@ def add_fib_at_start(arginput):
         end = max(max(start_end_pairs))
 
     assert start >= FLASH_BASE, ("Error - start 0x%x less than begining of user\
-	flash area" %start)
+    flash area" %start)
     # Compute checksum over the range (don't include data at location of crc)
     size = end - start + 1
     data = input_hex_file.tobinarray(start=start, size=size)
@@ -62,7 +66,7 @@ def add_fib_at_start(arginput):
     checksum = (start + size + crc32 + fw_rev) & 0xFFFFFFFF
 
     print("Writing FIB: base 0x%08X, size 0x%08X, crc32 0x%08X, fw rev 0x%08X,\
-	checksum 0x%08X" % (start, size, crc32, fw_rev, checksum))
+    checksum 0x%08X" % (start, size, crc32, fw_rev, checksum))
 
 #expected initial values used by daplink to validate that it is a valid bin
 #file added as dummy values in this file because the fib area preceeds the
@@ -80,18 +84,20 @@ def add_fib_at_start(arginput):
 
 #expected fib structure
 #typedef struct fib{
-	#uint32_t base;		/**< Base offset of firmware, indicating what flash the
-	#                        firmware is in. (will never be 0x11111111) */
-	#uint32_t size;		/**< Size of the firmware */
-	#uint32_t crc;		/**< CRC32 for firmware correctness check */
-	#uint32_t rev;		/**< Revision number */
-	#uint32_t checksum;	/**< Check-sum of information block */
+    #uint32_t base;     /**< Base offset of firmware, indicating what flash the
+    #                        firmware is in. (will never be 0x11111111) */
+    #uint32_t size;     /**< Size of the firmware */
+    #uint32_t crc;      /**< CRC32 for firmware correctness check */
+    #uint32_t rev;      /**< Revision number */
+    #uint32_t checksum; /**< Check-sum of information block */
 #}fib_t, *fib_pt;
 
     fib_start = FIB_BASE
     dummy_fib_size = 20
     fib_size = 20
+    trim_size = 24
     user_code_start = FLASH_BASE
+    trim_area_start = TRIM_BASE
 
     # Write FIB to the file in little endian
     output_hex_file[fib_start + 0] = (dummy_sp >> 0) & 0xFF
@@ -146,7 +152,51 @@ def add_fib_at_start(arginput):
     output_hex_file[fib_start + 39] = (checksum >> 24) & 0xFF
 
     #pad the rest of the file
-    for i in range(fib_start + dummy_fib_size + fib_size, user_code_start):
+    for i in range(fib_start + dummy_fib_size + fib_size, trim_area_start):
+        output_hex_file[i] = 0xFF
+
+    # add trim data from json
+    with open('./mbed-os/targets/TARGET_ONSEMI/TARGET_NCS36510/ncs36510_user_trim.json') as json_data:
+        trimdata = json.load(json_data)
+        mac_addr_low = int(trimdata["mac-addr-low"], 16)
+        mac_addr_high = int(trimdata["mac-addr-high"], 16)
+        clk_32k_trim = int(trimdata["32KHz-clk-trim"], 16)
+        clk_32m_trim = int(trimdata["32MHz-clk-trim"], 16)
+        rssi_trim = int(trimdata["rssi-trim"], 16)
+        txtune = int(trimdata["txtune-trim"], 16)
+
+    output_hex_file[trim_area_start + 0] = mac_addr_low & 0xFF
+    output_hex_file[trim_area_start + 1] = (mac_addr_low >> 8)  & 0xFF
+    output_hex_file[trim_area_start + 2] = (mac_addr_low >> 16) & 0xFF
+    output_hex_file[trim_area_start + 3] = (mac_addr_low >> 24) & 0xFF
+
+    output_hex_file[trim_area_start + 4] = mac_addr_high & 0xFF
+    output_hex_file[trim_area_start + 5] = (mac_addr_high >> 8)  & 0xFF
+    output_hex_file[trim_area_start + 6] = (mac_addr_high >> 16) & 0xFF
+    output_hex_file[trim_area_start + 7] = (mac_addr_high >> 24) & 0xFF
+
+    output_hex_file[trim_area_start + 8] = clk_32k_trim & 0xFF
+    output_hex_file[trim_area_start + 9] = (clk_32k_trim >> 8)  & 0xFF
+    output_hex_file[trim_area_start + 10] = (clk_32k_trim >> 16) & 0xFF
+    output_hex_file[trim_area_start + 11] = (clk_32k_trim >> 24) & 0xFF
+
+    output_hex_file[trim_area_start + 12] = clk_32m_trim & 0xFF
+    output_hex_file[trim_area_start + 13] = (clk_32m_trim >> 8)  & 0xFF
+    output_hex_file[trim_area_start + 14] = (clk_32m_trim >> 16) & 0xFF
+    output_hex_file[trim_area_start + 15] = (clk_32m_trim >> 24) & 0xFF
+
+    output_hex_file[trim_area_start + 16] = rssi_trim & 0xFF
+    output_hex_file[trim_area_start + 17] = (rssi_trim >> 8)  & 0xFF
+    output_hex_file[trim_area_start + 18] = (rssi_trim >> 16) & 0xFF
+    output_hex_file[trim_area_start + 19] = (rssi_trim >> 24) & 0xFF
+
+    output_hex_file[trim_area_start + 20] = txtune & 0xFF
+    output_hex_file[trim_area_start + 21] = (txtune >> 8)  & 0xFF
+    output_hex_file[trim_area_start + 22] = (txtune >> 16) & 0xFF
+    output_hex_file[trim_area_start + 23] = (txtune >> 24) & 0xFF
+
+    # pad the rest of the area with 0xFF
+    for i in range(trim_area_start + trim_size, user_code_start):
         output_hex_file[i] = 0xFF
 
     #merge two hex files
@@ -155,4 +205,3 @@ def add_fib_at_start(arginput):
     # Write out file(s)
     output_hex_file.tofile(file_name_hex, 'hex')
     output_hex_file.tofile(file_name_bin, 'bin')
-	

Original file line number	Diff line number	Diff line change
`@@ -101,10 +101,10 @@ void fncs36510_coma(void)`
`101`	`101`
`102`	`102`	`/** Trim the oscillators */`
`103`	`103`	`if ((TRIMREG->TRIM_32K_EXT & 0xFFFF0000) != 0xFFFF0000) {`
`104`		`- CLOCKREG->TRIM_32K_EXT = TRIMREG->TRIM_32K_EXT;`
	`104`	`+ CLOCKREG->TRIM_32K_EXT.WORD = TRIMREG->TRIM_32K_EXT;`
`105`	`105`	`}`
`106`	`106`	`if ((TRIMREG->TRIM_32M_EXT & 0xFFFF0000) != 0xFFFF0000) {`
`107`		`- CLOCKREG->TRIM_32M_EXT = TRIMREG->TRIM_32M_EXT;`
	`107`	`+ CLOCKREG->TRIM_32M_EXT.WORD = TRIMREG->TRIM_32M_EXT;`
`108`	`108`	`}`
`109`	`109`
`110`	`110`	`/* Enable UART 1 & 2 FIFO */`