Skip to content

Commit f0aed41

Browse files
committed
DISCO_L072CZ: remove dead code
1 parent 104295b commit f0aed41

File tree

1 file changed

+0
-3
lines changed
  • targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L072CZ_LRWAN1/device

1 file changed

+0
-3
lines changed

targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L072CZ_LRWAN1/device/system_clock.c

Lines changed: 0 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -200,11 +200,9 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
200200
// Output clock on MCO1 pin(PA8) for debugging purpose
201201
if (bypass == 0) { // Xtal used
202202
HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_2); // 16 MHz
203-
//HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz
204203
}
205204
else { // External clock used
206205
HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_4); // 8 MHz
207-
//HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_4); // 2 MHz
208206
}
209207
#endif
210208

@@ -278,7 +276,6 @@ uint8_t SetSysClock_PLL_HSI(void)
278276
#ifdef DEBUG_MCO
279277
// Output clock on MCO1 pin(PA8) for debugging purpose
280278
HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1); // 32 MHz (not precise due to HSI not calibrated)
281-
//HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz (not precise due to HSI not calibrated)
282279
#endif
283280

284281
return 1; // OK

0 commit comments

Comments
 (0)