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jeromecoutantjeromecoutant
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STM32H7: update target specific files with Cube-1.8
- startup files pdated from Cube - all SetSysClock aligned and checked - license header updated
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‎targets/TARGET_STM/README.md

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -69,7 +69,7 @@ This table summarizes the STM32Cube versions currently used in Mbed OS master br
6969
| F7 | 1.16.0 | https://github.com/STMicroelectronics/STM32CubeF7 |
7070
| G0 | 1.3.0 | https://github.com/STMicroelectronics/STM32CubeG0 |
7171
| G4 | 1.1.0 | https://github.com/STMicroelectronics/STM32CubeG4 |
72-
| H7 | 1.7.0 | https://github.com/STMicroelectronics/STM32CubeH7 |
72+
| H7 | 1.8.0 | https://github.com/STMicroelectronics/STM32CubeH7 |
7373
| L0 | 1.11.3 | https://github.com/STMicroelectronics/STM32CubeL0 |
7474
| L1 | 1.8.1 | https://github.com/STMicroelectronics/STM32CubeL1 |
7575
| L4 | 1.14.0 | https://github.com/STMicroelectronics/STM32CubeL4 |

‎targets/TARGET_STM/TARGET_STM32H7/PeripheralNames.h

Lines changed: 34 additions & 25 deletions
Original file line numberDiff line numberDiff line change
@@ -1,32 +1,18 @@
11
/* mbed Microcontroller Library
2-
*******************************************************************************
3-
* Copyright (c) 2016, STMicroelectronics
4-
* All rights reserved.
2+
* SPDX-License-Identifier: BSD-3-Clause
3+
******************************************************************************
54
*
6-
* Redistribution and use in source and binary forms, with or without
7-
* modification, are permitted provided that the following conditions are met:
5+
* Copyright (c) 2015-2020 STMicroelectronics.
6+
* All rights reserved.
87
*
9-
* 1. Redistributions of source code must retain the above copyright notice,
10-
* this list of conditions and the following disclaimer.
11-
* 2. Redistributions in binary form must reproduce the above copyright notice,
12-
* this list of conditions and the following disclaimer in the documentation
13-
* and/or other materials provided with the distribution.
14-
* 3. Neither the name of STMicroelectronics nor the names of its contributors
15-
* may be used to endorse or promote products derived from this software
16-
* without specific prior written permission.
8+
* This software component is licensed by ST under BSD 3-Clause license,
9+
* the "License"; You may not use this file except in compliance with the
10+
* License. You may obtain a copy of the License at:
11+
* opensource.org/licenses/BSD-3-Clause
1712
*
18-
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19-
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20-
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
21-
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
22-
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23-
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
24-
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
25-
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
26-
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27-
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28-
*******************************************************************************
13+
******************************************************************************
2914
*/
15+
3016
#ifndef MBED_PERIPHERALNAMES_H
3117
#define MBED_PERIPHERALNAMES_H
3218

@@ -39,11 +25,16 @@ extern "C" {
3925
typedef enum {
4026
ADC_1 = (int)ADC1_BASE,
4127
ADC_2 = (int)ADC2_BASE,
28+
#if ADC3_BASE
4229
ADC_3 = (int)ADC3_BASE
30+
#endif
4331
} ADCName;
4432

4533
typedef enum {
46-
DAC_1 = DAC1_BASE
34+
DAC_1 = DAC1_BASE,
35+
#if DAC2_BASE
36+
DAC_2 = DAC2_BASE,
37+
#endif
4738
} DACName;
4839

4940
typedef enum {
@@ -55,6 +46,12 @@ typedef enum {
5546
UART_6 = (int)USART6_BASE,
5647
UART_7 = (int)UART7_BASE,
5748
UART_8 = (int)UART8_BASE,
49+
#if UART9_BASE
50+
UART_9 = (int)UART9_BASE,
51+
#endif
52+
#if USART10_BASE
53+
UART_10 = (int)USART10_BASE,
54+
#endif
5855
LPUART_1 = (int)LPUART1_BASE
5956
} UARTName;
6057

@@ -76,7 +73,9 @@ typedef enum {
7673
} I2CName;
7774

7875
typedef enum {
76+
#if HRTIM1_BASE
7977
PWM_I = (int)HRTIM1_BASE,
78+
#endif
8079
PWM_1 = (int)TIM1_BASE,
8180
PWM_2 = (int)TIM2_BASE,
8281
PWM_3 = (int)TIM3_BASE,
@@ -97,11 +96,21 @@ typedef enum {
9796
} CANName;
9897

9998
typedef enum {
99+
#if QSPI_R_BASE
100100
QSPI_1 = (int)QSPI_R_BASE,
101+
#endif
102+
#if OCTOSPI1_R_BASE
103+
QSPI_1 = (int)OCTOSPI1_R_BASE,
104+
#endif
105+
#if OCTOSPI2_R_BASE
106+
QSPI_2 = (int)OCTOSPI2_R_BASE,
107+
#endif
101108
} QSPIName;
102109

103110
typedef enum {
111+
#if USB_OTG_FS_PERIPH_BASE
104112
USB_FS = (int)USB_OTG_FS_PERIPH_BASE,
113+
#endif
105114
USB_HS = (int)USB_OTG_HS_PERIPH_BASE
106115
} USBName;
107116

‎targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H743xI/TARGET_NUCLEO_H743ZI/system_clock.c

Lines changed: 25 additions & 29 deletions
Original file line numberDiff line numberDiff line change
@@ -1,17 +1,17 @@
1-
/*
2-
******************************************************************************
3-
* @attention
4-
*
5-
* <h2><center>&copy; Copyright (c) 2018-2019 STMicroelectronics.
6-
* All rights reserved.</center></h2>
7-
*
8-
* This software component is licensed by ST under BSD 3-Clause license,
9-
* the "License"; You may not use this file except in compliance with the
10-
* License. You may obtain a copy of the License at:
11-
* opensource.org/licenses/BSD-3-Clause
12-
*
13-
******************************************************************************
14-
*/
1+
/* mbed Microcontroller Library
2+
* SPDX-License-Identifier: BSD-3-Clause
3+
******************************************************************************
4+
*
5+
* Copyright (c) 2015-2020 STMicroelectronics.
6+
* All rights reserved.
7+
*
8+
* This software component is licensed by ST under BSD 3-Clause license,
9+
* the "License"; You may not use this file except in compliance with the
10+
* License. You may obtain a copy of the License at:
11+
* opensource.org/licenses/BSD-3-Clause
12+
*
13+
******************************************************************************
14+
*/
1515

1616
/**
1717
* This file configures the system clock as follows:
@@ -31,15 +31,8 @@
3131
**/
3232

3333
#include "stm32h7xx.h"
34-
#include "nvic_addr.h"
3534
#include "mbed_error.h"
3635

37-
/*!< Uncomment the following line if you need to relocate your vector Table in
38-
Internal SRAM. */
39-
/* #define VECT_TAB_SRAM */
40-
#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
41-
This value must be a multiple of 0x200. */
42-
4336
// clock source is selected with CLOCK_SOURCE in json config
4437
#define USE_PLL_HSE_EXTC 0x8 // Use external clock (ST Link MCO)
4538
#define USE_PLL_HSE_XTAL 0x4 // Use external xtal (X3 on board - not provided by default)
@@ -85,11 +78,12 @@ void SetSysClock(void)
8578
}
8679
}
8780

81+
8882
#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
8983
/******************************************************************************/
9084
/* PLL (clocked by HSE) used as System clock source */
9185
/******************************************************************************/
92-
uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
86+
MBED_WEAK uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
9387
{
9488
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
9589
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
@@ -112,8 +106,12 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
112106
RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
113107
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
114108
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
109+
#if HSE_VALUE==8000000
115110
RCC_OscInitStruct.PLL.PLLM = 4; // 2 MHz
116111
RCC_OscInitStruct.PLL.PLLN = 400; // 800 MHz
112+
#else
113+
#error Unsupported externall clock value, check HSE_VALUE define
114+
#endif
117115
RCC_OscInitStruct.PLL.PLLP = 2; // PLLCLK = SYSCLK = 400 MHz
118116
RCC_OscInitStruct.PLL.PLLQ = 80; // PLL1Q used for FDCAN = 10 MHz
119117
RCC_OscInitStruct.PLL.PLLR = 2;
@@ -164,9 +162,7 @@ uint8_t SetSysClock_PLL_HSI(void)
164162

165163
/*!< Supply configuration update enable */
166164
HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY);
167-
/* The voltage scaling allows optimizing the power consumption when the device is
168-
clocked below the maximum system frequency, to update the voltage scaling value
169-
regarding system frequency refer to product datasheet. */
165+
/* Configure the main internal regulator output voltage */
170166
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
171167
while (!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {}
172168

@@ -177,10 +173,10 @@ uint8_t SetSysClock_PLL_HSI(void)
177173
RCC_OscInitStruct.CSIState = RCC_CSI_OFF;
178174
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
179175
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
180-
RCC_OscInitStruct.PLL.PLLM = 8;
181-
RCC_OscInitStruct.PLL.PLLN = 100;
182-
RCC_OscInitStruct.PLL.PLLP = 2;
183-
RCC_OscInitStruct.PLL.PLLQ = 2;
176+
RCC_OscInitStruct.PLL.PLLM = 8; // 8 MHz
177+
RCC_OscInitStruct.PLL.PLLN = 100; // 800 MHz
178+
RCC_OscInitStruct.PLL.PLLP = 2; // 400 MHz
179+
RCC_OscInitStruct.PLL.PLLQ = 80; // PLL1Q used for FDCAN = 10 MHz
184180
RCC_OscInitStruct.PLL.PLLR = 2;
185181
RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE;
186182
RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_2;

‎targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H743xI/TARGET_NUCLEO_H743ZI2/system_clock.c

Lines changed: 29 additions & 38 deletions
Original file line numberDiff line numberDiff line change
@@ -1,17 +1,17 @@
1-
/*
2-
******************************************************************************
3-
* @attention
4-
*
5-
* <h2><center>&copy; Copyright (c) 2018-2019 STMicroelectronics.
6-
* All rights reserved.</center></h2>
7-
*
8-
* This software component is licensed by ST under BSD 3-Clause license,
9-
* the "License"; You may not use this file except in compliance with the
10-
* License. You may obtain a copy of the License at:
11-
* opensource.org/licenses/BSD-3-Clause
12-
*
13-
******************************************************************************
14-
*/
1+
/* mbed Microcontroller Library
2+
* SPDX-License-Identifier: BSD-3-Clause
3+
******************************************************************************
4+
*
5+
* Copyright (c) 2015-2020 STMicroelectronics.
6+
* All rights reserved.
7+
*
8+
* This software component is licensed by ST under BSD 3-Clause license,
9+
* the "License"; You may not use this file except in compliance with the
10+
* License. You may obtain a copy of the License at:
11+
* opensource.org/licenses/BSD-3-Clause
12+
*
13+
******************************************************************************
14+
*/
1515

1616
/**
1717
* This file configures the system clock as follows:
@@ -31,15 +31,8 @@
3131
**/
3232

3333
#include "stm32h7xx.h"
34-
#include "nvic_addr.h"
3534
#include "mbed_error.h"
3635

37-
/*!< Uncomment the following line if you need to relocate your vector Table in
38-
Internal SRAM. */
39-
/* #define VECT_TAB_SRAM */
40-
#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
41-
This value must be a multiple of 0x200. */
42-
4336
// clock source is selected with CLOCK_SOURCE in json config
4437
#define USE_PLL_HSE_EXTC 0x8 // Use external clock (ST Link MCO)
4538
#define USE_PLL_HSE_XTAL 0x4 // Use external xtal (X3 on board - not provided by default)
@@ -90,7 +83,7 @@ void SetSysClock(void)
9083
/******************************************************************************/
9184
/* PLL (clocked by HSE) used as System clock source */
9285
/******************************************************************************/
93-
uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
86+
MBED_WEAK uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
9487
{
9588
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
9689
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
@@ -110,18 +103,18 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
110103
} else {
111104
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
112105
}
113-
#if HSE_VALUE==8000000
114-
RCC_OscInitStruct.PLL.PLLM = 4; // 2 MHz
115-
RCC_OscInitStruct.PLL.PLLN = 480; // 960 MHz
116-
#elif HSE_VALUE==25000000
117-
RCC_OscInitStruct.PLL.PLLM = 5; // 5 MHz
118-
RCC_OscInitStruct.PLL.PLLN = 192; // 960 MHz
119-
#else
120-
#error Unsupported externall clock value, check hse_value define
121-
#endif
122106
RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
123107
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
124108
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
109+
#if HSE_VALUE==8000000
110+
RCC_OscInitStruct.PLL.PLLM = 4; // 2 MHz
111+
RCC_OscInitStruct.PLL.PLLN = 480; // 960 MHz
112+
#elif HSE_VALUE==25000000
113+
RCC_OscInitStruct.PLL.PLLM = 5; // 5 MHz
114+
RCC_OscInitStruct.PLL.PLLN = 192; // 960 MHz
115+
#else
116+
#error Unsupported externall clock value, check HSE_VALUE define
117+
#endif
125118
RCC_OscInitStruct.PLL.PLLP = 2; // PLLCLK = SYSCLK = 480 MHz
126119
RCC_OscInitStruct.PLL.PLLQ = 96; // PLL1Q used for FDCAN = 10 MHz
127120
RCC_OscInitStruct.PLL.PLLR = 2;
@@ -172,9 +165,7 @@ uint8_t SetSysClock_PLL_HSI(void)
172165

173166
/*!< Supply configuration update enable */
174167
HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY);
175-
/* The voltage scaling allows optimizing the power consumption when the device is
176-
clocked below the maximum system frequency, to update the voltage scaling value
177-
regarding system frequency refer to product datasheet. */
168+
/* Configure the main internal regulator output voltage */
178169
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
179170
while (!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {}
180171

@@ -185,10 +176,10 @@ uint8_t SetSysClock_PLL_HSI(void)
185176
RCC_OscInitStruct.CSIState = RCC_CSI_OFF;
186177
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
187178
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
188-
RCC_OscInitStruct.PLL.PLLM = 8;
189-
RCC_OscInitStruct.PLL.PLLN = 120;
190-
RCC_OscInitStruct.PLL.PLLP = 2;
191-
RCC_OscInitStruct.PLL.PLLQ = 2;
179+
RCC_OscInitStruct.PLL.PLLM = 8; // 8 MHz
180+
RCC_OscInitStruct.PLL.PLLN = 120; // 960 MHz
181+
RCC_OscInitStruct.PLL.PLLP = 2; // 480 MHz
182+
RCC_OscInitStruct.PLL.PLLQ = 96; // PLL1Q used for FDCAN = 10 MHz
192183
RCC_OscInitStruct.PLL.PLLR = 2;
193184
RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE;
194185
RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_2;

‎targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H743xI/TOOLCHAIN_ARM/stm32h743xI.sct

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -25,13 +25,13 @@
2525
#define MBED_APP_SIZE MBED_ROM_SIZE
2626
#endif
2727

28-
/* This value is normally defined by the tools to 0x1000 for bare metal and 0x400 for RTOS */
2928
#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE)
30-
# if defined(MBED_BOOT_STACK_SIZE)
31-
# define MBED_CONF_TARGET_BOOT_STACK_SIZE MBED_BOOT_STACK_SIZE
32-
# else
33-
# define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400
34-
# endif
29+
/* This value is normally defined by the tools to 0x1000 for bare metal and 0x400 for RTOS */
30+
#if defined(MBED_BOOT_STACK_SIZE)
31+
#define MBED_CONF_TARGET_BOOT_STACK_SIZE MBED_BOOT_STACK_SIZE
32+
#else
33+
#define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400
34+
#endif
3535
#endif
3636

3737
/* Round up VECTORS_SIZE to 8 bytes */

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