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ccli8adbridge
ccli8
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adbridge
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Check timer active flag after enabling timer counting in us_ticker/lp_ticker
1 parent 85a1139 commit f6ac93a

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8 files changed

+127
-70
lines changed

8 files changed

+127
-70
lines changed

‎targets/TARGET_NUVOTON/TARGET_M451/lp_ticker.c

Lines changed: 19 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -63,28 +63,35 @@ void lp_ticker_init(void)
6363
// Enable IP clock
6464
CLK_EnableModuleClock(TIMER_MODINIT.clkidx);
6565

66+
TIMER_T *timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname);
67+
6668
// Configure clock
67-
uint32_t clk_timer = TIMER_GetModuleClock((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
69+
uint32_t clk_timer = TIMER_GetModuleClock(timer_base);
6870
uint32_t prescale_timer = clk_timer / NU_TMRCLK_PER_SEC - 1;
6971
MBED_ASSERT((prescale_timer != (uint32_t) -1) && prescale_timer <= 127);
7072
MBED_ASSERT((clk_timer % NU_TMRCLK_PER_SEC) == 0);
7173
uint32_t cmp_timer = TMR_CMP_MAX;
7274
MBED_ASSERT(cmp_timer >= TMR_CMP_MIN && cmp_timer <= TMR_CMP_MAX);
7375
// Continuous mode
7476
// NOTE: TIMER_CTL_CNTDATEN_Msk exists in NUC472, but not in M451. In M451, TIMER_CNT is updated continuously by default.
75-
((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname))->CTL = TIMER_CONTINUOUS_MODE | prescale_timer/* | TIMER_CTL_CNTDATEN_Msk*/;
76-
((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname))->CMP = cmp_timer;
77+
timer_base->CTL = TIMER_CONTINUOUS_MODE | prescale_timer/* | TIMER_CTL_CNTDATEN_Msk*/;
78+
79+
timer_base->CMP = cmp_timer;
7780

7881
// Set vector
7982
NVIC_SetVector(TIMER_MODINIT.irq_n, (uint32_t) TIMER_MODINIT.var);
8083

8184
NVIC_EnableIRQ(TIMER_MODINIT.irq_n);
8285

83-
TIMER_EnableInt((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
84-
TIMER_EnableWakeup((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
85-
/* NOTE: When engine is clocked by low power clock source (LXT/LIRC), we need to wait for 3 engine clocks. */
86+
TIMER_EnableInt(timer_base);
87+
88+
TIMER_EnableWakeup(timer_base);
8689
wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3);
87-
TIMER_Start((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
90+
91+
TIMER_Start(timer_base);
92+
93+
/* Wait for timer to start counting and raise active flag */
94+
while(! (timer_base->CTL & TIMER_CTL_ACTSTS_Msk));
8895
}
8996

9097
timestamp_t lp_ticker_read()
@@ -93,7 +100,7 @@ timestamp_t lp_ticker_read()
93100
lp_ticker_init();
94101
}
95102

96-
TIMER_T * timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname);
103+
TIMER_T *timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname);
97104

98105
return (TIMER_GetCounter(timer_base) / NU_TMRCLK_PER_TICK);
99106
}
@@ -108,12 +115,13 @@ void lp_ticker_set_interrupt(timestamp_t timestamp)
108115
* This behavior is not what we want. To fix it, we could configure new CMP value
109116
* without stopping counting first.
110117
*/
111-
TIMER_T * timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname);
118+
TIMER_T *timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname);
112119

113120
/* NOTE: Because H/W timer requests min compare value, our implementation would have alarm delay of
114121
* (TMR_CMP_MIN - interval_clk) clocks when interval_clk is between [1, TMR_CMP_MIN). */
115122
uint32_t cmp_timer = timestamp * NU_TMRCLK_PER_TICK;
116123
cmp_timer = NU_CLAMP(cmp_timer, TMR_CMP_MIN, TMR_CMP_MAX);
124+
117125
timer_base->CMP = cmp_timer;
118126
wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3);
119127
}
@@ -147,8 +155,9 @@ const ticker_info_t* lp_ticker_get_info()
147155
static void tmr1_vec(void)
148156
{
149157
TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
158+
150159
TIMER_ClearWakeupFlag((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
151-
160+
152161
// NOTE: lp_ticker_set_interrupt() may get called in lp_ticker_irq_handler();
153162
lp_ticker_irq_handler();
154163
}

‎targets/TARGET_NUVOTON/TARGET_M451/us_ticker.c

Lines changed: 12 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -58,23 +58,28 @@ void us_ticker_init(void)
5858
// Enable IP clock
5959
CLK_EnableModuleClock(TIMER_MODINIT.clkidx);
6060

61+
TIMER_T *timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname);
62+
6163
// Timer for normal counter
62-
uint32_t clk_timer = TIMER_GetModuleClock((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
64+
uint32_t clk_timer = TIMER_GetModuleClock(timer_base);
6365
uint32_t prescale_timer = clk_timer / NU_TMRCLK_PER_SEC - 1;
6466
MBED_ASSERT((prescale_timer != (uint32_t) -1) && prescale_timer <= 127);
6567
MBED_ASSERT((clk_timer % NU_TMRCLK_PER_SEC) == 0);
6668
uint32_t cmp_timer = TMR_CMP_MAX;
6769
MBED_ASSERT(cmp_timer >= TMR_CMP_MIN && cmp_timer <= TMR_CMP_MAX);
6870
// NOTE: TIMER_CTL_CNTDATEN_Msk exists in NUC472, but not in M451. In M451, TIMER_CNT is updated continuously by default.
69-
((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname))->CTL = TIMER_CONTINUOUS_MODE | prescale_timer/* | TIMER_CTL_CNTDATEN_Msk*/;
70-
((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname))->CMP = cmp_timer;
71+
timer_base->CTL = TIMER_CONTINUOUS_MODE | prescale_timer/* | TIMER_CTL_CNTDATEN_Msk*/;
72+
timer_base->CMP = cmp_timer;
7173

7274
NVIC_SetVector(TIMER_MODINIT.irq_n, (uint32_t) TIMER_MODINIT.var);
7375

7476
NVIC_EnableIRQ(TIMER_MODINIT.irq_n);
7577

76-
TIMER_EnableInt((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
77-
TIMER_Start((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
78+
TIMER_EnableInt(timer_base);
79+
80+
TIMER_Start(timer_base);
81+
/* Wait for timer to start counting and raise active flag */
82+
while(! (timer_base->CTL & TIMER_CTL_ACTSTS_Msk));
7883
}
7984

8085
uint32_t us_ticker_read()
@@ -83,7 +88,7 @@ uint32_t us_ticker_read()
8388
us_ticker_init();
8489
}
8590

86-
TIMER_T * timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname);
91+
TIMER_T *timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname);
8792

8893
return (TIMER_GetCounter(timer_base) / NU_TMRCLK_PER_TICK);
8994
}
@@ -98,7 +103,7 @@ void us_ticker_set_interrupt(timestamp_t timestamp)
98103
* This behavior is not what we want. To fix it, we could configure new CMP value
99104
* without stopping counting first.
100105
*/
101-
TIMER_T * timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname);
106+
TIMER_T *timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname);
102107

103108
/* NOTE: Because H/W timer requests min compare value, our implementation would have alarm delay of
104109
* (TMR_CMP_MIN - interval_clk) clocks when interval_clk is between [1, TMR_CMP_MIN). */

‎targets/TARGET_NUVOTON/TARGET_M480/lp_ticker.c

Lines changed: 19 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -63,28 +63,35 @@ void lp_ticker_init(void)
6363
// Enable IP clock
6464
CLK_EnableModuleClock(TIMER_MODINIT.clkidx);
6565

66+
TIMER_T *timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname);
67+
6668
// Configure clock
67-
uint32_t clk_timer = TIMER_GetModuleClock((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
69+
uint32_t clk_timer = TIMER_GetModuleClock(timer_base);
6870
uint32_t prescale_timer = clk_timer / NU_TMRCLK_PER_SEC - 1;
6971
MBED_ASSERT((prescale_timer != (uint32_t) -1) && prescale_timer <= 127);
7072
MBED_ASSERT((clk_timer % NU_TMRCLK_PER_SEC) == 0);
7173
uint32_t cmp_timer = TMR_CMP_MAX;
7274
MBED_ASSERT(cmp_timer >= TMR_CMP_MIN && cmp_timer <= TMR_CMP_MAX);
7375
// Continuous mode
7476
// NOTE: TIMER_CTL_CNTDATEN_Msk exists in NUC472, but not in M451/M480. In M451/M480, TIMER_CNT is updated continuously by default.
75-
((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname))->CTL = TIMER_CONTINUOUS_MODE | prescale_timer/* | TIMER_CTL_CNTDATEN_Msk*/;
76-
((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname))->CMP = cmp_timer;
77+
timer_base->CTL = TIMER_CONTINUOUS_MODE | prescale_timer/* | TIMER_CTL_CNTDATEN_Msk*/;
78+
79+
timer_base->CMP = cmp_timer;
7780

7881
// Set vector
7982
NVIC_SetVector(TIMER_MODINIT.irq_n, (uint32_t) TIMER_MODINIT.var);
8083

8184
NVIC_EnableIRQ(TIMER_MODINIT.irq_n);
8285

83-
TIMER_EnableInt((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
84-
TIMER_EnableWakeup((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
85-
/* NOTE: When engine is clocked by low power clock source (LXT/LIRC), we need to wait for 3 engine clocks. */
86+
TIMER_EnableInt(timer_base);
87+
88+
TIMER_EnableWakeup(timer_base);
8689
wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3);
87-
TIMER_Start((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
90+
91+
TIMER_Start(timer_base);
92+
93+
/* Wait for timer to start counting and raise active flag */
94+
while(! (timer_base->CTL & TIMER_CTL_ACTSTS_Msk));
8895
}
8996

9097
timestamp_t lp_ticker_read()
@@ -93,7 +100,7 @@ timestamp_t lp_ticker_read()
93100
lp_ticker_init();
94101
}
95102

96-
TIMER_T * timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname);
103+
TIMER_T *timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname);
97104

98105
return (TIMER_GetCounter(timer_base) / NU_TMRCLK_PER_TICK);
99106
}
@@ -108,12 +115,13 @@ void lp_ticker_set_interrupt(timestamp_t timestamp)
108115
* This behavior is not what we want. To fix it, we could configure new CMP value
109116
* without stopping counting first.
110117
*/
111-
TIMER_T * timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname);
118+
TIMER_T *timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname);
112119

113120
/* NOTE: Because H/W timer requests min compare value, our implementation would have alarm delay of
114121
* (TMR_CMP_MIN - interval_clk) clocks when interval_clk is between [1, TMR_CMP_MIN). */
115122
uint32_t cmp_timer = timestamp * NU_TMRCLK_PER_TICK;
116123
cmp_timer = NU_CLAMP(cmp_timer, TMR_CMP_MIN, TMR_CMP_MAX);
124+
117125
timer_base->CMP = cmp_timer;
118126
wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3);
119127
}
@@ -147,8 +155,9 @@ const ticker_info_t* lp_ticker_get_info()
147155
static void tmr1_vec(void)
148156
{
149157
TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
158+
150159
TIMER_ClearWakeupFlag((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
151-
160+
152161
// NOTE: lp_ticker_set_interrupt() may get called in lp_ticker_irq_handler();
153162
lp_ticker_irq_handler();
154163
}

‎targets/TARGET_NUVOTON/TARGET_M480/us_ticker.c

Lines changed: 12 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -58,23 +58,28 @@ void us_ticker_init(void)
5858
// Enable IP clock
5959
CLK_EnableModuleClock(TIMER_MODINIT.clkidx);
6060

61+
TIMER_T *timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname);
62+
6163
// Timer for normal counter
62-
uint32_t clk_timer = TIMER_GetModuleClock((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
64+
uint32_t clk_timer = TIMER_GetModuleClock(timer_base);
6365
uint32_t prescale_timer = clk_timer / NU_TMRCLK_PER_SEC - 1;
6466
MBED_ASSERT((prescale_timer != (uint32_t) -1) && prescale_timer <= 127);
6567
MBED_ASSERT((clk_timer % NU_TMRCLK_PER_SEC) == 0);
6668
uint32_t cmp_timer = TMR_CMP_MAX;
6769
MBED_ASSERT(cmp_timer >= TMR_CMP_MIN && cmp_timer <= TMR_CMP_MAX);
6870
// NOTE: TIMER_CTL_CNTDATEN_Msk exists in NUC472, but not in M451/M480. In M451/M480, TIMER_CNT is updated continuously by default.
69-
((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname))->CTL = TIMER_CONTINUOUS_MODE | prescale_timer/* | TIMER_CTL_CNTDATEN_Msk*/;
70-
((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname))->CMP = cmp_timer;
71+
timer_base->CTL = TIMER_CONTINUOUS_MODE | prescale_timer/* | TIMER_CTL_CNTDATEN_Msk*/;
72+
timer_base->CMP = cmp_timer;
7173

7274
NVIC_SetVector(TIMER_MODINIT.irq_n, (uint32_t) TIMER_MODINIT.var);
7375

7476
NVIC_EnableIRQ(TIMER_MODINIT.irq_n);
7577

76-
TIMER_EnableInt((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
77-
TIMER_Start((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
78+
TIMER_EnableInt(timer_base);
79+
80+
TIMER_Start(timer_base);
81+
/* Wait for timer to start counting and raise active flag */
82+
while(! (timer_base->CTL & TIMER_CTL_ACTSTS_Msk));
7883
}
7984

8085
uint32_t us_ticker_read()
@@ -83,7 +88,7 @@ uint32_t us_ticker_read()
8388
us_ticker_init();
8489
}
8590

86-
TIMER_T * timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname);
91+
TIMER_T *timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname);
8792

8893
return (TIMER_GetCounter(timer_base) / NU_TMRCLK_PER_TICK);
8994
}
@@ -98,7 +103,7 @@ void us_ticker_set_interrupt(timestamp_t timestamp)
98103
* This behavior is not what we want. To fix it, we could configure new CMP value
99104
* without stopping counting first.
100105
*/
101-
TIMER_T * timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname);
106+
TIMER_T *timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname);
102107

103108
/* NOTE: Because H/W timer requests min compare value, our implementation would have alarm delay of
104109
* (TMR_CMP_MIN - interval_clk) clocks when interval_clk is between [1, TMR_CMP_MIN). */

‎targets/TARGET_NUVOTON/TARGET_NANO100/lp_ticker.c

Lines changed: 21 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -65,28 +65,36 @@ void lp_ticker_init(void)
6565
// Enable IP clock
6666
CLK_EnableModuleClock(TIMER_MODINIT.clkidx);
6767

68+
TIMER_T *timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname);
69+
6870
// Configure clock
69-
uint32_t clk_timer = TIMER_GetModuleClock((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
71+
uint32_t clk_timer = TIMER_GetModuleClock(timer_base);
7072
uint32_t prescale_timer = clk_timer / NU_TMRCLK_PER_SEC - 1;
7173
MBED_ASSERT((prescale_timer != (uint32_t) -1) && prescale_timer <= 127);
7274
MBED_ASSERT((clk_timer % NU_TMRCLK_PER_SEC) == 0);
7375
uint32_t cmp_timer = TMR_CMP_MAX;
7476
MBED_ASSERT(cmp_timer >= TMR_CMP_MIN && cmp_timer <= TMR_CMP_MAX);
7577
// Continuous mode
76-
((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname))->CTL = TIMER_CONTINUOUS_MODE;
77-
((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname))->PRECNT = prescale_timer;
78-
((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname))->CMPR = cmp_timer;
78+
timer_base->CTL = TIMER_CONTINUOUS_MODE;
79+
80+
timer_base->PRECNT = prescale_timer;
81+
82+
timer_base->CMPR = cmp_timer;
7983

8084
// Set vector
8185
NVIC_SetVector(TIMER_MODINIT.irq_n, (uint32_t) TIMER_MODINIT.var);
8286

8387
NVIC_EnableIRQ(TIMER_MODINIT.irq_n);
8488

85-
TIMER_EnableInt((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
86-
TIMER_EnableWakeup((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
87-
/* NOTE: When engine is clocked by low power clock source (LXT/LIRC), we need to wait for 3 engine clocks. */
89+
TIMER_EnableInt(timer_base);
90+
91+
TIMER_EnableWakeup(timer_base);
8892
wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3);
89-
TIMER_Start((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
93+
94+
TIMER_Start(timer_base);
95+
96+
/* Wait for timer to start counting and raise active flag */
97+
while(! (timer_base->CTL & TIMER_CTL_TMR_ACT_Msk));
9098
}
9199

92100
timestamp_t lp_ticker_read()
@@ -95,7 +103,7 @@ timestamp_t lp_ticker_read()
95103
lp_ticker_init();
96104
}
97105

98-
TIMER_T * timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname);
106+
TIMER_T *timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname);
99107

100108
return (TIMER_GetCounter(timer_base) / NU_TMRCLK_PER_TICK);
101109
}
@@ -110,12 +118,13 @@ void lp_ticker_set_interrupt(timestamp_t timestamp)
110118
* This behavior is not what we want. To fix it, we could configure new CMP value
111119
* without stopping counting first.
112120
*/
113-
TIMER_T * timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname);
121+
TIMER_T *timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname);
114122

115123
/* NOTE: Because H/W timer requests min compare value, our implementation would have alarm delay of
116124
* (TMR_CMP_MIN - interval_clk) clocks when interval_clk is between [1, TMR_CMP_MIN). */
117125
uint32_t cmp_timer = timestamp * NU_TMRCLK_PER_TICK;
118126
cmp_timer = NU_CLAMP(cmp_timer, TMR_CMP_MIN, TMR_CMP_MAX);
127+
119128
timer_base->CMPR = cmp_timer;
120129
wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3);
121130
}
@@ -149,8 +158,9 @@ const ticker_info_t* lp_ticker_get_info()
149158
void TMR1_IRQHandler(void)
150159
{
151160
TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
161+
152162
TIMER_ClearWakeupFlag((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
153-
163+
154164
// NOTE: lp_ticker_set_interrupt() may get called in lp_ticker_irq_handler();
155165
lp_ticker_irq_handler();
156166
}

‎targets/TARGET_NUVOTON/TARGET_NANO100/us_ticker.c

Lines changed: 13 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -60,23 +60,28 @@ void us_ticker_init(void)
6060
// Enable IP clock
6161
CLK_EnableModuleClock(TIMER_MODINIT.clkidx);
6262

63+
TIMER_T *timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname);
64+
6365
// Timer for normal counter
64-
uint32_t clk_timer = TIMER_GetModuleClock((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
66+
uint32_t clk_timer = TIMER_GetModuleClock(timer_base);
6567
uint32_t prescale_timer = clk_timer / NU_TMRCLK_PER_SEC - 1;
6668
MBED_ASSERT((prescale_timer != (uint32_t) -1) && prescale_timer <= 127);
6769
MBED_ASSERT((clk_timer % NU_TMRCLK_PER_SEC) == 0);
6870
uint32_t cmp_timer = TMR_CMP_MAX;
6971
MBED_ASSERT(cmp_timer >= TMR_CMP_MIN && cmp_timer <= TMR_CMP_MAX);
70-
((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname))->CTL = TIMER_CONTINUOUS_MODE;
71-
((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname))->PRECNT = prescale_timer;
72-
((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname))->CMPR = cmp_timer;
72+
timer_base->CTL = TIMER_CONTINUOUS_MODE;
73+
timer_base->PRECNT = prescale_timer;
74+
timer_base->CMPR = cmp_timer;
7375

7476
NVIC_SetVector(TIMER_MODINIT.irq_n, (uint32_t) TIMER_MODINIT.var);
7577

7678
NVIC_EnableIRQ(TIMER_MODINIT.irq_n);
7779

78-
TIMER_EnableInt((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
79-
TIMER_Start((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
80+
TIMER_EnableInt(timer_base);
81+
82+
TIMER_Start(timer_base);
83+
/* Wait for timer to start counting and raise active flag */
84+
while(! (timer_base->CTL & TIMER_CTL_TMR_ACT_Msk));
8085
}
8186

8287
uint32_t us_ticker_read()
@@ -85,7 +90,7 @@ uint32_t us_ticker_read()
8590
us_ticker_init();
8691
}
8792

88-
TIMER_T * timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname);
93+
TIMER_T *timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname);
8994

9095
return (TIMER_GetCounter(timer_base) / NU_TMRCLK_PER_TICK);
9196
}
@@ -100,7 +105,7 @@ void us_ticker_set_interrupt(timestamp_t timestamp)
100105
* This behavior is not what we want. To fix it, we could configure new CMP value
101106
* without stopping counting first.
102107
*/
103-
TIMER_T * timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname);
108+
TIMER_T *timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname);
104109

105110
/* NOTE: Because H/W timer requests min compare value, our implementation would have alarm delay of
106111
* (TMR_CMP_MIN - interval_clk) clocks when interval_clk is between [1, TMR_CMP_MIN). */

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