|
1 | 1 | {% extends "mcuxpresso/.cproject.tmpl" %}
|
2 | 2 |
|
3 |
| -{% block cpu_config %}{% endblock %} |
| 3 | +{% block cpu_config %}<?xml version="1.0" encoding="UTF-8"?> |
| 4 | +<TargetConfig> |
| 5 | +<Properties property_3="NXP" property_4="LPC54608J512" property_count="5" version="70200"/> |
| 6 | +<infoList vendor="NXP"><info chip="LPC54608J512" name="LPC54608J512"><chip><name>LPC54608J512</name> |
| 7 | +<family>LPC546xx</family> |
| 8 | +<vendor>NXP</vendor> |
| 9 | +<memory can_program="true" id="Flash" is_ro="true" size="512" type="Flash"/> |
| 10 | +<memory id="RAM" size="200" type="RAM"/> |
| 11 | +<memoryInstance derived_from="Flash" driver="LPC5460x_512K.cfx" id="PROGRAM_FLASH" location="0x0" size="0x80000"/> |
| 12 | +<memoryInstance derived_from="RAM" id="SRAM_0_1_2_3" location="0x20000000" size="0x28000"/> |
| 13 | +<memoryInstance derived_from="RAM" id="SRAMX" location="0x4000000" size="0x8000"/> |
| 14 | +<memoryInstance derived_from="RAM" id="USB_RAM" location="0x40100000" size="0x2000"/> |
| 15 | +<peripheralInstance derived_from="SYSCON" id="SYSCON" location="0x40000000"/> |
| 16 | +<peripheralInstance derived_from="IOCON" id="IOCON" location="0x40001000"/> |
| 17 | +<peripheralInstance derived_from="GINT0" id="GINT0" location="0x40002000"/> |
| 18 | +<peripheralInstance derived_from="GINT1" id="GINT1" location="0x40003000"/> |
| 19 | +<peripheralInstance derived_from="PINT" id="PINT" location="0x40004000"/> |
| 20 | +<peripheralInstance derived_from="INPUTMUX" id="INPUTMUX" location="0x40005000"/> |
| 21 | +<peripheralInstance derived_from="CTIMER0" id="CTIMER0" location="0x40008000"/> |
| 22 | +<peripheralInstance derived_from="CTIMER1" id="CTIMER1" location="0x40009000"/> |
| 23 | +<peripheralInstance derived_from="CTIMER2" id="CTIMER2" location="0x40028000"/> |
| 24 | +<peripheralInstance derived_from="CTIMER3" id="CTIMER3" location="0x40048000"/> |
| 25 | +<peripheralInstance derived_from="CTIMER4" id="CTIMER4" location="0x40049000"/> |
| 26 | +<peripheralInstance derived_from="WWDT" id="WWDT" location="0x4000C000"/> |
| 27 | +<peripheralInstance derived_from="MRT0" id="MRT0" location="0x4000D000"/> |
| 28 | +<peripheralInstance derived_from="UTICK0" id="UTICK0" location="0x4000E000"/> |
| 29 | +<peripheralInstance derived_from="EEPROM" id="EEPROM" location="0x40014000"/> |
| 30 | +<peripheralInstance derived_from="OTPC" id="OTPC" location="0x40015000"/> |
| 31 | +<peripheralInstance derived_from="RTC" id="RTC" location="0x4002C000"/> |
| 32 | +<peripheralInstance derived_from="RIT" id="RIT" location="0x4002D000"/> |
| 33 | +<peripheralInstance derived_from="FMC" id="FMC" location="0x40034000"/> |
| 34 | +<peripheralInstance derived_from="SMARTCARD0" id="SMARTCARD0" location="0x40036000"/> |
| 35 | +<peripheralInstance derived_from="SMARTCARD1" id="SMARTCARD1" location="0x40037000"/> |
| 36 | +<peripheralInstance derived_from="ASYNC_SYSCON" id="ASYNC_SYSCON" location="0x40040000"/> |
| 37 | +<peripheralInstance derived_from="SPIFI0" id="SPIFI0" location="0x40080000"/> |
| 38 | +<peripheralInstance derived_from="EMC" id="EMC" location="0x40081000"/> |
| 39 | +<peripheralInstance derived_from="DMA0" id="DMA0" location="0x40082000"/> |
| 40 | +<peripheralInstance derived_from="LCD" id="LCD" location="0x40083000"/> |
| 41 | +<peripheralInstance derived_from="USB0" id="USB0" location="0x40084000"/> |
| 42 | +<peripheralInstance derived_from="SCT0" id="SCT0" location="0x40085000"/> |
| 43 | +<peripheralInstance derived_from="SPI0" id="SPI0" location="0x40086000"/> |
| 44 | +<peripheralInstance derived_from="SPI1" id="SPI1" location="0x40087000"/> |
| 45 | +<peripheralInstance derived_from="SPI2" id="SPI2" location="0x40088000"/> |
| 46 | +<peripheralInstance derived_from="SPI3" id="SPI3" location="0x40089000"/> |
| 47 | +<peripheralInstance derived_from="SPI4" id="SPI4" location="0x4008A000"/> |
| 48 | +<peripheralInstance derived_from="SPI5" id="SPI5" location="0x40096000"/> |
| 49 | +<peripheralInstance derived_from="SPI6" id="SPI6" location="0x40097000"/> |
| 50 | +<peripheralInstance derived_from="SPI7" id="SPI7" location="0x40098000"/> |
| 51 | +<peripheralInstance derived_from="SPI8" id="SPI8" location="0x40099000"/> |
| 52 | +<peripheralInstance derived_from="SPI9" id="SPI9" location="0x4009A000"/> |
| 53 | +<peripheralInstance derived_from="FLEXCOMM0" id="FLEXCOMM0" location="0x40086000"/> |
| 54 | +<peripheralInstance derived_from="FLEXCOMM1" id="FLEXCOMM1" location="0x40087000"/> |
| 55 | +<peripheralInstance derived_from="FLEXCOMM2" id="FLEXCOMM2" location="0x40088000"/> |
| 56 | +<peripheralInstance derived_from="FLEXCOMM3" id="FLEXCOMM3" location="0x40089000"/> |
| 57 | +<peripheralInstance derived_from="FLEXCOMM4" id="FLEXCOMM4" location="0x4008A000"/> |
| 58 | +<peripheralInstance derived_from="FLEXCOMM5" id="FLEXCOMM5" location="0x40096000"/> |
| 59 | +<peripheralInstance derived_from="FLEXCOMM6" id="FLEXCOMM6" location="0x40097000"/> |
| 60 | +<peripheralInstance derived_from="FLEXCOMM7" id="FLEXCOMM7" location="0x40098000"/> |
| 61 | +<peripheralInstance derived_from="FLEXCOMM8" id="FLEXCOMM8" location="0x40099000"/> |
| 62 | +<peripheralInstance derived_from="FLEXCOMM9" id="FLEXCOMM9" location="0x4009A000"/> |
| 63 | +<peripheralInstance derived_from="I2C0" id="I2C0" location="0x40086000"/> |
| 64 | +<peripheralInstance derived_from="I2C1" id="I2C1" location="0x40087000"/> |
| 65 | +<peripheralInstance derived_from="I2C2" id="I2C2" location="0x40088000"/> |
| 66 | +<peripheralInstance derived_from="I2C3" id="I2C3" location="0x40089000"/> |
| 67 | +<peripheralInstance derived_from="I2C4" id="I2C4" location="0x4008A000"/> |
| 68 | +<peripheralInstance derived_from="I2C5" id="I2C5" location="0x40096000"/> |
| 69 | +<peripheralInstance derived_from="I2C6" id="I2C6" location="0x40097000"/> |
| 70 | +<peripheralInstance derived_from="I2C7" id="I2C7" location="0x40098000"/> |
| 71 | +<peripheralInstance derived_from="I2C8" id="I2C8" location="0x40099000"/> |
| 72 | +<peripheralInstance derived_from="I2C9" id="I2C9" location="0x4009A000"/> |
| 73 | +<peripheralInstance derived_from="USART0" id="USART0" location="0x40086000"/> |
| 74 | +<peripheralInstance derived_from="USART1" id="USART1" location="0x40087000"/> |
| 75 | +<peripheralInstance derived_from="USART2" id="USART2" location="0x40088000"/> |
| 76 | +<peripheralInstance derived_from="USART3" id="USART3" location="0x40089000"/> |
| 77 | +<peripheralInstance derived_from="USART4" id="USART4" location="0x4008A000"/> |
| 78 | +<peripheralInstance derived_from="USART5" id="USART5" location="0x40096000"/> |
| 79 | +<peripheralInstance derived_from="USART6" id="USART6" location="0x40097000"/> |
| 80 | +<peripheralInstance derived_from="USART7" id="USART7" location="0x40098000"/> |
| 81 | +<peripheralInstance derived_from="USART8" id="USART8" location="0x40099000"/> |
| 82 | +<peripheralInstance derived_from="USART9" id="USART9" location="0x4009A000"/> |
| 83 | +<peripheralInstance derived_from="GPIO" id="GPIO" location="0x4008C000"/> |
| 84 | +<peripheralInstance derived_from="DMIC0" id="DMIC0" location="0x40090000"/> |
| 85 | +<peripheralInstance derived_from="ENET" id="ENET" location="0x40092000"/> |
| 86 | +<peripheralInstance derived_from="USBHSD" id="USBHSD" location="0x40094000"/> |
| 87 | +<peripheralInstance derived_from="CRC_ENGINE" id="CRC_ENGINE" location="0x40095000"/> |
| 88 | +<peripheralInstance derived_from="I2S0" id="I2S0" location="0x40097000"/> |
| 89 | +<peripheralInstance derived_from="I2S1" id="I2S1" location="0x40098000"/> |
| 90 | +<peripheralInstance derived_from="SDIF" id="SDIF" location="0x4009B000"/> |
| 91 | +<peripheralInstance derived_from="CAN0" id="CAN0" location="0x4009D000"/> |
| 92 | +<peripheralInstance derived_from="CAN1" id="CAN1" location="0x4009E000"/> |
| 93 | +<peripheralInstance derived_from="ADC0" id="ADC0" location="0x400A0000"/> |
| 94 | +<peripheralInstance derived_from="USBFSH" id="USBFSH" location="0x400A2000"/> |
| 95 | +<peripheralInstance derived_from="USBHSH" id="USBHSH" location="0x400A3000"/> |
| 96 | +</chip> |
| 97 | +<processor><name gcc_name="cortex-m4">Cortex-M4</name> |
| 98 | +<family>Cortex-M</family> |
| 99 | +</processor> |
| 100 | +<link href="LPC54608_internal_peripheral.xml" show="embed" type="simple"/> |
| 101 | +</info> |
| 102 | +</infoList> |
| 103 | +</TargetConfig>{% endblock %} |
0 commit comments