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Arto KinnunenCruz Monrreal II
Arto Kinnunen
authored and
Cruz Monrreal II
committed
Use Mbed OS coding style
Run astyle 3.0 for the changed c-files.
1 parent c7c0af8 commit fc73e45

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4 files changed

+36
-28
lines changed

4 files changed

+36
-28
lines changed

‎targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/spi_api.c‎

Lines changed: 10 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -32,7 +32,8 @@ static SPI_Type *const spi_address[] = SPI_BASE_PTRS;
3232
/* Array of SPI bus clock frequencies */
3333
static clock_name_t const spi_clocks[] = SPI_CLOCK_FREQS;
3434

35-
SPIName spi_get_peripheral_name(PinName mosi, PinName miso, PinName sclk) {
35+
SPIName spi_get_peripheral_name(PinName mosi, PinName miso, PinName sclk)
36+
{
3637
SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI);
3738
SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO);
3839
SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK);
@@ -113,7 +114,7 @@ void spi_frequency(spi_t *obj, int hz)
113114
DSPI_MasterSetDelayTimes(spi_address[obj->instance], kDSPI_Ctar0, kDSPI_LastSckToPcs, busClock, 500000000 / hz);
114115
}
115116

116-
static inline int spi_readable(spi_t * obj)
117+
static inline int spi_readable(spi_t *obj)
117118
{
118119
return (DSPI_GetStatusFlags(spi_address[obj->instance]) & kDSPI_RxFifoDrainRequestFlag);
119120
}
@@ -137,17 +138,18 @@ int spi_master_write(spi_t *obj, int value)
137138
}
138139

139140
int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length,
140-
char *rx_buffer, int rx_length, char write_fill) {
141+
char *rx_buffer, int rx_length, char write_fill)
142+
{
141143
int total = (tx_length > rx_length) ? tx_length : rx_length;
142144

143145
// Default write is done in each and every call, in future can create HAL API instead
144146
DSPI_SetDummyData(spi_address[obj->instance], write_fill);
145147

146-
DSPI_MasterTransferBlocking(spi_address[obj->instance], &(dspi_transfer_t){
147-
.txData = (uint8_t *)tx_buffer,
148-
.rxData = (uint8_t *)rx_buffer,
149-
.dataSize = total,
150-
.configFlags = kDSPI_MasterCtar0 | kDSPI_MasterPcs0 | kDSPI_MasterPcsContinuous,
148+
DSPI_MasterTransferBlocking(spi_address[obj->instance], &(dspi_transfer_t) {
149+
.txData = (uint8_t *)tx_buffer,
150+
.rxData = (uint8_t *)rx_buffer,
151+
.dataSize = total,
152+
.configFlags = kDSPI_MasterCtar0 | kDSPI_MasterPcs0 | kDSPI_MasterPcsContinuous,
151153
});
152154

153155
DSPI_ClearStatusFlags(spi_address[obj->instance], kDSPI_RxFifoDrainRequestFlag | kDSPI_EndOfQueueFlag);

‎targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/spi_api.c‎

Lines changed: 5 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -32,7 +32,8 @@ static SPI_Type *const spi_address[] = SPI_BASE_PTRS;
3232
/* Array of SPI bus clock frequencies */
3333
static clock_name_t const spi_clocks[] = SPI_CLOCK_FREQS;
3434

35-
SPIName spi_get_peripheral_name(PinName mosi, PinName miso, PinName sclk) {
35+
SPIName spi_get_peripheral_name(PinName mosi, PinName miso, PinName sclk)
36+
{
3637
SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI);
3738
SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO);
3839
SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK);
@@ -112,7 +113,7 @@ void spi_frequency(spi_t *obj, int hz)
112113
DSPI_MasterSetDelayTimes(spi_address[obj->instance], kDSPI_Ctar0, kDSPI_LastSckToPcs, busClock, 500000000 / hz);
113114
}
114115

115-
static inline int spi_readable(spi_t * obj)
116+
static inline int spi_readable(spi_t *obj)
116117
{
117118
return (DSPI_GetStatusFlags(spi_address[obj->instance]) & kDSPI_RxFifoDrainRequestFlag);
118119
}
@@ -136,7 +137,8 @@ int spi_master_write(spi_t *obj, int value)
136137
}
137138

138139
int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length,
139-
char *rx_buffer, int rx_length, char write_fill) {
140+
char *rx_buffer, int rx_length, char write_fill)
141+
{
140142
int total = (tx_length > rx_length) ? tx_length : rx_length;
141143

142144
for (int i = 0; i < total; i++) {

‎targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW41Z/spi_api.c‎

Lines changed: 5 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -32,7 +32,8 @@ static SPI_Type *const spi_address[] = SPI_BASE_PTRS;
3232
/* Array of SPI bus clock frequencies */
3333
static clock_name_t const spi_clocks[] = SPI_CLOCK_FREQS;
3434

35-
SPIName spi_get_peripheral_name(PinName mosi, PinName miso, PinName sclk) {
35+
SPIName spi_get_peripheral_name(PinName mosi, PinName miso, PinName sclk)
36+
{
3637
SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI);
3738
SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO);
3839
SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK);
@@ -112,7 +113,7 @@ void spi_frequency(spi_t *obj, int hz)
112113
DSPI_MasterSetDelayTimes(spi_address[obj->instance], kDSPI_Ctar0, kDSPI_LastSckToPcs, busClock, 500000000 / hz);
113114
}
114115

115-
static inline int spi_readable(spi_t * obj)
116+
static inline int spi_readable(spi_t *obj)
116117
{
117118
return (DSPI_GetStatusFlags(spi_address[obj->instance]) & kDSPI_RxFifoDrainRequestFlag);
118119
}
@@ -136,7 +137,8 @@ int spi_master_write(spi_t *obj, int value)
136137
}
137138

138139
int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length,
139-
char *rx_buffer, int rx_length, char write_fill) {
140+
char *rx_buffer, int rx_length, char write_fill)
141+
{
140142
int total = (tx_length > rx_length) ? tx_length : rx_length;
141143

142144
for (int i = 0; i < total; i++) {

‎targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/spi_api.c‎

Lines changed: 16 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -33,7 +33,8 @@ static SPI_Type *const spi_address[] = SPI_BASE_PTRS;
3333
/* Array of SPI bus clock frequencies */
3434
static clock_name_t const spi_clocks[] = SPI_CLOCK_FREQS;
3535

36-
SPIName spi_get_peripheral_name(PinName mosi, PinName miso, PinName sclk) {
36+
SPIName spi_get_peripheral_name(PinName mosi, PinName miso, PinName sclk)
37+
{
3738
SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI);
3839
SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO);
3940
SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK);
@@ -122,7 +123,7 @@ void spi_frequency(spi_t *obj, int hz)
122123
DSPI_MasterSetDelayTimes(spi_address[obj->spi.instance], kDSPI_Ctar0, kDSPI_LastSckToPcs, busClock, 500000000 / hz);
123124
}
124125

125-
static inline int spi_readable(spi_t * obj)
126+
static inline int spi_readable(spi_t *obj)
126127
{
127128
return (DSPI_GetStatusFlags(spi_address[obj->spi.instance]) & kDSPI_RxFifoDrainRequestFlag);
128129
}
@@ -146,17 +147,18 @@ int spi_master_write(spi_t *obj, int value)
146147
}
147148

148149
int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length,
149-
char *rx_buffer, int rx_length, char write_fill) {
150+
char *rx_buffer, int rx_length, char write_fill)
151+
{
150152
int total = (tx_length > rx_length) ? tx_length : rx_length;
151153

152154
// Default write is done in each and every call, in future can create HAL API instead
153155
DSPI_SetDummyData(spi_address[obj->spi.instance], write_fill);
154156

155-
DSPI_MasterTransferBlocking(spi_address[obj->spi.instance], &(dspi_transfer_t){
156-
.txData = (uint8_t *)tx_buffer,
157-
.rxData = (uint8_t *)rx_buffer,
158-
.dataSize = total,
159-
.configFlags = kDSPI_MasterCtar0 | kDSPI_MasterPcs0 | kDSPI_MasterPcsContinuous,
157+
DSPI_MasterTransferBlocking(spi_address[obj->spi.instance], &(dspi_transfer_t) {
158+
.txData = (uint8_t *)tx_buffer,
159+
.rxData = (uint8_t *)rx_buffer,
160+
.dataSize = total,
161+
.configFlags = kDSPI_MasterCtar0 | kDSPI_MasterPcs0 | kDSPI_MasterPcsContinuous,
160162
});
161163

162164
DSPI_ClearStatusFlags(spi_address[obj->spi.instance], kDSPI_RxFifoDrainRequestFlag | kDSPI_EndOfQueueFlag);
@@ -199,7 +201,7 @@ static int32_t spi_master_transfer_asynch(spi_t *obj)
199201
obj->spi.status = kDSPI_Busy;
200202

201203
if (obj->spi.spiDmaMasterRx.dmaUsageState == DMA_USAGE_ALLOCATED ||
202-
obj->spi.spiDmaMasterRx.dmaUsageState == DMA_USAGE_TEMPORARY_ALLOCATED) {
204+
obj->spi.spiDmaMasterRx.dmaUsageState == DMA_USAGE_TEMPORARY_ALLOCATED) {
203205
status = DSPI_MasterTransferEDMA(spi_address[obj->spi.instance], &obj->spi.spi_dma_master_handle, &masterXfer);
204206
if (status == kStatus_DSPI_OutOfRange) {
205207
if (obj->spi.bits > 8) {
@@ -331,14 +333,14 @@ static void spi_buffer_set(spi_t *obj, const void *tx, uint32_t tx_length, void
331333

332334
void spi_master_transfer(spi_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint8_t bit_width, uint32_t handler, uint32_t event, DMAUsage hint)
333335
{
334-
if(spi_active(obj)) {
336+
if (spi_active(obj)) {
335337
return;
336338
}
337339

338340
/* check corner case */
339-
if(tx_length == 0) {
341+
if (tx_length == 0) {
340342
tx_length = rx_length;
341-
tx = (void*) 0;
343+
tx = (void *) 0;
342344
}
343345

344346
/* First, set the buffer */
@@ -439,13 +441,13 @@ uint32_t spi_irq_handler_asynch(spi_t *obj)
439441
void spi_abort_asynch(spi_t *obj)
440442
{
441443
// If we're not currently transferring, then there's nothing to do here
442-
if(spi_active(obj) == 0) {
444+
if (spi_active(obj) == 0) {
443445
return;
444446
}
445447

446448
// Determine whether we're running DMA or interrupt
447449
if (obj->spi.spiDmaMasterRx.dmaUsageState == DMA_USAGE_ALLOCATED ||
448-
obj->spi.spiDmaMasterRx.dmaUsageState == DMA_USAGE_TEMPORARY_ALLOCATED) {
450+
obj->spi.spiDmaMasterRx.dmaUsageState == DMA_USAGE_TEMPORARY_ALLOCATED) {
449451
DSPI_MasterTransferAbortEDMA(spi_address[obj->spi.instance], &obj->spi.spi_dma_master_handle);
450452
/* Release the dma channels if they were opportunistically allocated */
451453
if (obj->spi.spiDmaMasterRx.dmaUsageState == DMA_USAGE_TEMPORARY_ALLOCATED) {

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