arch/ARM/cotrex_m: preelaborate some units

Author: Fabien-Chouteau

arch/ARM/cortex_m/src/cortex_m-cache.ads

@@ -35,6 +35,7 @@
 with System;
 
 package Cortex_M.Cache is
+   pragma Elaborate_Body;
 
    procedure Enable_I_Cache;
 

arch/ARM/cortex_m/src/cortex_m-debug.ads

@@ -30,6 +30,7 @@
 ------------------------------------------------------------------------------
 
 package Cortex_M.Debug is
+   pragma Preelaborate;
 
    function Halting_Debug_Enabled return Boolean;
 

arch/ARM/cortex_m/src/cortex_m-dwt.ads

@@ -51,10 +51,14 @@ package Cortex_M.DWT is  --  Data Watchpoint Trace
    --  below. The values are just the NUMCOMP nibble and the boolean flags in
    --  the next nibble.
    No_DWT_Present                            : constant UInt32 := 0;
-   Only_One_Comparator                       : constant UInt32 := 16#1000_0000#;  --  268435456 dec
-   One_Comparator_Watchpoints                : constant UInt32 := 16#1F00_0000#;  --  520093696 dec
-   Four_Comparators_Watchpoints_And_Triggers : constant UInt32 := 16#4000_0000#;  -- 1073741824 dec
-   Four_Comparators_Watchpoints_Only         : constant UInt32 := 16#4F00_0000#;  -- 1325400064 dec
+   Only_One_Comparator                       : constant UInt32 :=
+      16#1000_0000#; --  268435456 dec
+   One_Comparator_Watchpoints                : constant UInt32 :=
+      16#1F00_0000#; --  520093696 dec
+   Four_Comparators_Watchpoints_And_Triggers : constant UInt32 :=
+      16#4000_0000#; -- 1073741824 dec
+   Four_Comparators_Watchpoints_Only         : constant UInt32 :=
+      16#4F00_0000#; -- 1325400064 dec
 
    function DWT_Reset_Value return UInt32 with Inline;
    --  Returns the value of the DWT.CTRL register as a word, for convenient

arch/ARM/cortex_m/src/cortex_m-hints.ads

@@ -39,6 +39,7 @@
 --    https://developer.arm.com/documentation/ddi0419/e
 
 package Cortex_M.Hints is
+   pragma Preelaborate;
 
    procedure Send_Event with Inline;
    --  A6.7.57 SEV

arch/ARM/cortex_m/src/fpu/cortex_m-fpu.ads

@@ -47,6 +47,7 @@
 with HAL; use HAL;
 
 package Cortex_M.FPU is
+   pragma Preelaborate;
 
    function Sqrt (X : Float) return Float;
 

arch/ARM/cortex_m/src/memory_barriers.adb

@@ -44,4 +44,3 @@ package body Memory_Barriers is
    end Data_Synchronization_Barrier;
 
 end Memory_Barriers;
-

arch/ARM/cortex_m/src/memory_barriers.ads

@@ -32,11 +32,11 @@
 --  This file provides utility functions for ARM Cortex microcontrollers
 
 package Memory_Barriers is
+   pragma Preelaborate;
 
    procedure Data_Synchronization_Barrier with Inline;
    --  Injects instruction "DSB Sy" i.e., a "full system" domain barrier
 
    procedure DSB renames Data_Synchronization_Barrier;
 
 end Memory_Barriers;
-

arch/ARM/cortex_m/src/nvic_cm0/cortex_m-nvic.ads

@@ -45,6 +45,7 @@
 with HAL;                  use HAL;
 
 package Cortex_M.NVIC is  -- the Nested Vectored Interrupt Controller
+   pragma Preelaborate;
 
    NVIC_PRIO_BITS : constant := 2;
    --  All Cortex M0 parts have 2 bit priority mask

arch/ARM/cortex_m/src/nvic_cm4_cm7/cortex_m-nvic.adb

@@ -99,7 +99,8 @@ package body Cortex_M.NVIC is
       Subpriority      : Interrupt_Priority)
       return Interrupt_Priority
    is
-      PriorityGroupTmp    : constant Interrupt_Priority := Priority_Group and 16#07#;
+      PriorityGroupTmp    : constant Interrupt_Priority :=
+         Priority_Group and 16#07#;
       PreemptPriorityBits : Interrupt_Priority;
       SubPriorityBits     : Interrupt_Priority;
       Temp1 : Interrupt_Priority;
@@ -251,4 +252,3 @@ package body Cortex_M.NVIC is
    end Reset_System;
 
 end Cortex_M.NVIC;
-

arch/ARM/cortex_m/src/nvic_cm4_cm7/cortex_m-nvic.ads

@@ -46,6 +46,7 @@ with System;
 with HAL;            use HAL;
 
 package Cortex_M.NVIC is  -- the Nested Vectored Interrupt Controller
+   pragma Elaborate_Body;
 
    type Interrupt_ID is new Natural range 0 .. 240;
    type Interrupt_Priority is new UInt32;
@@ -65,7 +66,6 @@ package Cortex_M.NVIC is  -- the Nested Vectored Interrupt Controller
    --  4 bits for pre-emption priority;  0 bits for subpriority
    Priority_Group_4 : constant UInt32 := 16#00000003#;
 
-
    procedure Set_Priority_Grouping (Priority_Group : Interrupt_Priority)
      with Inline;
 
@@ -110,7 +110,6 @@ private
    type Words is array (Natural range <>) of UInt32;
    type UInt8s is array (Natural range <>) of UInt8;
 
-
    type Nested_Vectored_Interrupt_Controller is record
       ISER      : Words (0 .. 7);
       --  Interrupt Set Enable Register
@@ -151,7 +150,6 @@ private
       STIR      at 3584 range 0 .. 31;     -- 4 UInt8s
    end record;
 
-
    type System_Control_Block is record
       CPUID     : UInt32;
       --  CPUID Base Register   (read-only)
@@ -221,7 +219,6 @@ private
       CPACR     at 136 range 0 .. 31;              -- Offset: 0x088
    end record;
 
-
    SCS_Base  : constant := 16#E000_E000#;
    --  system control space base address
    NVIC_Base : constant := SCS_Base +  16#0100#;
@@ -238,7 +235,6 @@ private
      Address => System'To_Address (NVIC_Base);
    pragma Import (Ada, NVIC);
 
-
    SCB_AIRCR_PRIGROUP_Pos  : constant := 8;
    SCB_AIRCR_PRIGROUP_Mask : constant UInt32 :=
      Shift_Left (7, SCB_AIRCR_PRIGROUP_Pos);