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| 1 | +------------------------------------------------------------------------------ |
| 2 | +-- -- |
| 3 | +-- Copyright (C) 2023, AdaCore -- |
| 4 | +-- -- |
| 5 | +-- Redistribution and use in source and binary forms, with or without -- |
| 6 | +-- modification, are permitted provided that the following conditions are -- |
| 7 | +-- met: -- |
| 8 | +-- 1. Redistributions of source code must retain the above copyright -- |
| 9 | +-- notice, this list of conditions and the following disclaimer. -- |
| 10 | +-- 2. Redistributions in binary form must reproduce the above copyright -- |
| 11 | +-- notice, this list of conditions and the following disclaimer in -- |
| 12 | +-- the documentation and/or other materials provided with the -- |
| 13 | +-- distribution. -- |
| 14 | +-- 3. Neither the name of STMicroelectronics nor the names of its -- |
| 15 | +-- contributors may be used to endorse or promote products derived -- |
| 16 | +-- from this software without specific prior written permission. -- |
| 17 | +-- -- |
| 18 | +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -- |
| 19 | +-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -- |
| 20 | +-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -- |
| 21 | +-- A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -- |
| 22 | +-- HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -- |
| 23 | +-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -- |
| 24 | +-- LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -- |
| 25 | +-- DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -- |
| 26 | +-- THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -- |
| 27 | +-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -- |
| 28 | +-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -- |
| 29 | +-- -- |
| 30 | +------------------------------------------------------------------------------ |
| 31 | + |
| 32 | +-- Flexible Static Memory Controller in STM32F40x/41x family |
| 33 | + |
| 34 | +with System; |
| 35 | + |
| 36 | +package STM32.FSMC is |
| 37 | + |
| 38 | + subtype Clock_Cycle_Count is Natural; |
| 39 | + -- Number of AHB clock cycles (HCLK) |
| 40 | + |
| 41 | + -- Bank 1 supports NOR Flash, PSRAM and SRAM. |
| 42 | + type Memory_Type is (SRAM, PSRAM, NOR_Flash); |
| 43 | + type Memory_Bus_Width is (Byte, Half_Word); -- 8 or 16 bit |
| 44 | + type Signal_Kind is (None, Positive, Negative); |
| 45 | + |
| 46 | + type Asynchronous_Extended_Mode is (Mode_A, Mode_B, Mode_C, Mode_D, None); |
| 47 | + -- See extended mode definitions in STM32F40x/41x datasheet. |
| 48 | + -- None corresponds to Mode 1 or Mode 2 depending on the type of memory. |
| 49 | + -- Extended modes have a dedicated settings for write operations, while |
| 50 | + -- Mode 1, 2 have shared settings for read/write. |
| 51 | + |
| 52 | + type Asynchronous_Extended_Configuration |
| 53 | + (Mode : Asynchronous_Extended_Mode := None) is |
| 54 | + record |
| 55 | + case Mode is |
| 56 | + when None => |
| 57 | + null; |
| 58 | + |
| 59 | + when others => |
| 60 | + Write_Bus_Turn : Clock_Cycle_Count range 0 .. 15; |
| 61 | + Write_Data_Setup : Clock_Cycle_Count range 1 .. 256; |
| 62 | + Write_Address_Setup : Clock_Cycle_Count range 0 .. 15; |
| 63 | + |
| 64 | + case Mode is |
| 65 | + when Mode_D => |
| 66 | + Read_Address_Hold : Clock_Cycle_Count range 0 .. 15; |
| 67 | + Write_Address_Hold : Clock_Cycle_Count range 0 .. 15; |
| 68 | + |
| 69 | + when others => |
| 70 | + null; |
| 71 | + end case; |
| 72 | + end case; |
| 73 | + end record; |
| 74 | + |
| 75 | + type Asynchronous_Configuration is record |
| 76 | + Wait_Signal : Signal_Kind := None; |
| 77 | + Write_Enable : Boolean := False; |
| 78 | + Bus_Width : Memory_Bus_Width := Byte; |
| 79 | + Memory_Type : FSMC.Memory_Type; |
| 80 | + Bus_Turn : Clock_Cycle_Count range 0 .. 15 := 15; |
| 81 | + Data_Setup : Clock_Cycle_Count range 1 .. 255 := 255; |
| 82 | + Address_Setup : Clock_Cycle_Count range 0 .. 15 := 15; |
| 83 | + |
| 84 | + Extended : Asynchronous_Extended_Configuration := (Mode => None); |
| 85 | + -- Additional settings |
| 86 | + end record; |
| 87 | + -- Configuration of the subbank of Bank 1. Not every combination of memory |
| 88 | + -- type and extended mode is allowed. Corresponding predicate is: |
| 89 | + -- with Predicate => |
| 90 | + -- (if Memory_Type = NOR_Flash then Extended.Mode /= Mode_A |
| 91 | + -- else Extended.Mode not in Mode_B | Mode_C); |
| 92 | + |
| 93 | + type NOR_PSRAM_Configuration (Is_Set : Boolean := False) is record |
| 94 | + case Is_Set is |
| 95 | + when True => |
| 96 | + Value : Asynchronous_Configuration; |
| 97 | + when False => |
| 98 | + null; |
| 99 | + end case; |
| 100 | + end record; |
| 101 | + |
| 102 | + subtype Subbank_Index is Integer range 1 .. 4; |
| 103 | + -- Bank 1 has 4 sub-banks |
| 104 | + |
| 105 | + type Bank_1_Configuration is array (Subbank_Index) of NOR_PSRAM_Configuration; |
| 106 | + |
| 107 | + type NAND_PC_Card_Configuration (Is_Set : Boolean := False) is record |
| 108 | + null; -- TBD |
| 109 | + end record; |
| 110 | + -- Bank 2, 3 supports NAND flash, Bank 4 - PC Card |
| 111 | + -- These are not yet implemented |
| 112 | + |
| 113 | + procedure Configure |
| 114 | + (Bank_1 : Bank_1_Configuration := (1 .. 4 => (Is_Set => False)); |
| 115 | + Bank_2 : NAND_PC_Card_Configuration := (Is_Set => False); |
| 116 | + Bank_3 : NAND_PC_Card_Configuration := (Is_Set => False); |
| 117 | + Bank_4 : NAND_PC_Card_Configuration := (Is_Set => False)); |
| 118 | + -- Configure memory banks |
| 119 | + |
| 120 | + function Bank_1_Start |
| 121 | + (Subbank : Subbank_Index := 1) return System.Address is |
| 122 | + (case Subbank is |
| 123 | + when 1 => System'To_Address (16#6000_0000#), |
| 124 | + when 2 => System'To_Address (16#6400_0000#), |
| 125 | + when 3 => System'To_Address (16#6800_0000#), |
| 126 | + when 4 => System'To_Address (16#6C00_0000#)); |
| 127 | + |
| 128 | + Bank_2_Start : constant System.Address := |
| 129 | + System'To_Address (16#7000_0000#); |
| 130 | + |
| 131 | + Bank_3_Start : constant System.Address := |
| 132 | + System'To_Address (16#8000_0000#); |
| 133 | + |
| 134 | + Bank_4_Start : constant System.Address := |
| 135 | + System'To_Address (16#9000_0000#); |
| 136 | + |
| 137 | +end STM32.FSMC; |
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