AMDGPU: Disable AGPR selection in mfma rewrite test

This makes the test actually test the intended rewrite
pass. Also add some tests with inline immediates in src2.
Switch the target to gfx942 for future test functions.

Author: arsenm

llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr.ll

@@ -1,13 +1,16 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
-; RUN: llc -mcpu=gfx90a < %s | FileCheck %s
+; RUN: llc -mcpu=gfx942 -amdgpu-mfma-vgpr-form < %s | FileCheck %s
 
 target triple = "amdgcn-amd-amdhsa"
 
 define amdgpu_kernel void @test_mfma_f32_32x32x1f32_rewrite_vgpr_mfma(ptr addrspace(1) %arg) #0 {
 ; CHECK-LABEL: test_mfma_f32_32x32x1f32_rewrite_vgpr_mfma:
 ; CHECK:       ; %bb.0: ; %bb
 ; CHECK-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; CHECK-NEXT:    v_and_b32_e32 v0, 0x3ff, v0
 ; CHECK-NEXT:    v_lshlrev_b32_e32 v0, 7, v0
+; CHECK-NEXT:    v_mov_b32_e32 v32, 1.0
+; CHECK-NEXT:    v_mov_b32_e32 v33, 2.0
 ; CHECK-NEXT:    s_waitcnt lgkmcnt(0)
 ; CHECK-NEXT:    global_load_dwordx4 v[28:31], v0, s[0:1] offset:112
 ; CHECK-NEXT:    global_load_dwordx4 v[24:27], v0, s[0:1] offset:96
@@ -18,117 +21,58 @@ define amdgpu_kernel void @test_mfma_f32_32x32x1f32_rewrite_vgpr_mfma(ptr addrsp
 ; CHECK-NEXT:    global_load_dwordx4 v[4:7], v0, s[0:1] offset:16
 ; CHECK-NEXT:    s_nop 0
 ; CHECK-NEXT:    global_load_dwordx4 v[0:3], v0, s[0:1]
+; CHECK-NEXT:    v_accvgpr_write_b32 a0, 1.0
+; CHECK-NEXT:    v_accvgpr_write_b32 a1, 2.0
 ; CHECK-NEXT:    s_waitcnt vmcnt(0)
-; CHECK-NEXT:    v_accvgpr_write_b32 a0, v0
-; CHECK-NEXT:    v_accvgpr_write_b32 a1, v1
-; CHECK-NEXT:    v_accvgpr_write_b32 a2, v2
-; CHECK-NEXT:    v_accvgpr_write_b32 a3, v3
-; CHECK-NEXT:    v_accvgpr_write_b32 a4, v4
-; CHECK-NEXT:    v_accvgpr_write_b32 a5, v5
-; CHECK-NEXT:    v_accvgpr_write_b32 a6, v6
-; CHECK-NEXT:    v_accvgpr_write_b32 a7, v7
-; CHECK-NEXT:    v_accvgpr_write_b32 a8, v8
-; CHECK-NEXT:    v_accvgpr_write_b32 a9, v9
-; CHECK-NEXT:    v_accvgpr_write_b32 a10, v10
-; CHECK-NEXT:    v_accvgpr_write_b32 a11, v11
-; CHECK-NEXT:    v_accvgpr_write_b32 a12, v12
-; CHECK-NEXT:    v_accvgpr_write_b32 a13, v13
-; CHECK-NEXT:    v_accvgpr_write_b32 a14, v14
-; CHECK-NEXT:    v_accvgpr_write_b32 a15, v15
-; CHECK-NEXT:    v_accvgpr_write_b32 a16, v16
-; CHECK-NEXT:    v_accvgpr_write_b32 a17, v17
-; CHECK-NEXT:    v_accvgpr_write_b32 a18, v18
-; CHECK-NEXT:    v_accvgpr_write_b32 a19, v19
-; CHECK-NEXT:    v_accvgpr_write_b32 a20, v20
-; CHECK-NEXT:    v_accvgpr_write_b32 a21, v21
-; CHECK-NEXT:    v_accvgpr_write_b32 a22, v22
-; CHECK-NEXT:    v_accvgpr_write_b32 a23, v23
-; CHECK-NEXT:    v_accvgpr_write_b32 a24, v24
-; CHECK-NEXT:    v_accvgpr_write_b32 a25, v25
-; CHECK-NEXT:    v_accvgpr_write_b32 a26, v26
-; CHECK-NEXT:    v_accvgpr_write_b32 a27, v27
-; CHECK-NEXT:    v_accvgpr_write_b32 a28, v28
-; CHECK-NEXT:    v_accvgpr_write_b32 a29, v29
-; CHECK-NEXT:    v_accvgpr_write_b32 a30, v30
-; CHECK-NEXT:    v_accvgpr_write_b32 a31, v31
-; CHECK-NEXT:    v_mov_b32_e32 v0, 1.0
-; CHECK-NEXT:    v_mov_b32_e32 v1, 2.0
-; CHECK-NEXT:    s_nop 1
-; CHECK-NEXT:    v_mfma_f32_32x32x1f32 a[0:31], v0, v1, a[0:31]
-; CHECK-NEXT:    v_mfma_f32_32x32x1f32 a[32:63], v0, v1, a[0:31]
+; CHECK-NEXT:    v_mfma_f32_32x32x1_2b_f32 v[0:31], v32, v33, v[0:31]
+; CHECK-NEXT:    v_mfma_f32_32x32x1_2b_f32 v[32:63], a0, a1, v[0:31]
 ; CHECK-NEXT:    s_nop 7
 ; CHECK-NEXT:    s_nop 7
-; CHECK-NEXT:    s_nop 2
-; CHECK-NEXT:    v_accvgpr_read_b32 v4, a59
-; CHECK-NEXT:    v_accvgpr_read_b32 v5, a58
-; CHECK-NEXT:    v_accvgpr_read_b32 v6, a57
-; CHECK-NEXT:    v_accvgpr_read_b32 v7, a56
-; CHECK-NEXT:    v_accvgpr_read_b32 v8, a55
-; CHECK-NEXT:    v_accvgpr_read_b32 v9, a54
-; CHECK-NEXT:    v_accvgpr_read_b32 v10, a53
-; CHECK-NEXT:    v_accvgpr_read_b32 v11, a52
-; CHECK-NEXT:    v_accvgpr_read_b32 v12, a51
-; CHECK-NEXT:    v_accvgpr_read_b32 v13, a50
-; CHECK-NEXT:    v_accvgpr_read_b32 v14, a49
-; CHECK-NEXT:    v_accvgpr_read_b32 v15, a48
-; CHECK-NEXT:    v_accvgpr_read_b32 v16, a47
-; CHECK-NEXT:    v_accvgpr_read_b32 v17, a46
-; CHECK-NEXT:    v_accvgpr_read_b32 v18, a45
-; CHECK-NEXT:    v_accvgpr_read_b32 v19, a44
-; CHECK-NEXT:    v_accvgpr_read_b32 v20, a43
-; CHECK-NEXT:    v_accvgpr_read_b32 v21, a42
-; CHECK-NEXT:    v_accvgpr_read_b32 v22, a41
-; CHECK-NEXT:    v_accvgpr_read_b32 v23, a40
-; CHECK-NEXT:    v_accvgpr_read_b32 v24, a39
-; CHECK-NEXT:    v_accvgpr_read_b32 v25, a38
-; CHECK-NEXT:    v_accvgpr_read_b32 v26, a37
-; CHECK-NEXT:    v_accvgpr_read_b32 v27, a36
-; CHECK-NEXT:    v_accvgpr_read_b32 v28, a35
-; CHECK-NEXT:    v_accvgpr_read_b32 v29, a34
-; CHECK-NEXT:    v_accvgpr_mov_b32 a2, a32
-; CHECK-NEXT:    v_accvgpr_mov_b32 a3, a33
-; CHECK-NEXT:    v_accvgpr_write_b32 a4, v29
-; CHECK-NEXT:    v_accvgpr_write_b32 a5, v28
-; CHECK-NEXT:    v_accvgpr_write_b32 a6, v27
-; CHECK-NEXT:    v_accvgpr_write_b32 a7, v26
-; CHECK-NEXT:    v_accvgpr_write_b32 a8, v25
-; CHECK-NEXT:    v_accvgpr_write_b32 a9, v24
-; CHECK-NEXT:    v_accvgpr_write_b32 a10, v23
-; CHECK-NEXT:    v_accvgpr_write_b32 a11, v22
-; CHECK-NEXT:    v_accvgpr_write_b32 a12, v21
-; CHECK-NEXT:    v_accvgpr_write_b32 a13, v20
-; CHECK-NEXT:    v_accvgpr_write_b32 a14, v19
-; CHECK-NEXT:    v_accvgpr_write_b32 a15, v18
-; CHECK-NEXT:    v_accvgpr_write_b32 a16, v17
-; CHECK-NEXT:    v_accvgpr_write_b32 a17, v16
-; CHECK-NEXT:    v_accvgpr_write_b32 a18, v15
-; CHECK-NEXT:    v_accvgpr_write_b32 a19, v14
-; CHECK-NEXT:    v_accvgpr_write_b32 a20, v13
-; CHECK-NEXT:    v_accvgpr_write_b32 a21, v12
-; CHECK-NEXT:    v_accvgpr_write_b32 a22, v11
-; CHECK-NEXT:    v_accvgpr_write_b32 a23, v10
-; CHECK-NEXT:    v_accvgpr_write_b32 a24, v9
-; CHECK-NEXT:    v_accvgpr_write_b32 a25, v8
-; CHECK-NEXT:    v_accvgpr_write_b32 a26, v7
-; CHECK-NEXT:    v_accvgpr_write_b32 a27, v6
-; CHECK-NEXT:    v_accvgpr_write_b32 a28, v5
-; CHECK-NEXT:    v_accvgpr_write_b32 a29, v4
-; CHECK-NEXT:    v_accvgpr_mov_b32 a30, a60
-; CHECK-NEXT:    v_accvgpr_mov_b32 a31, a61
 ; CHECK-NEXT:    s_nop 1
-; CHECK-NEXT:    v_mfma_f32_32x32x1f32 a[0:31], v0, v1, a[0:31]
-; CHECK-NEXT:    v_mov_b32_e32 v0, 0
+; CHECK-NEXT:    v_mov_b32_e32 v2, v32
+; CHECK-NEXT:    v_mov_b32_e32 v3, v33
+; CHECK-NEXT:    v_mov_b32_e32 v4, v34
+; CHECK-NEXT:    v_mov_b32_e32 v5, v35
+; CHECK-NEXT:    v_mov_b32_e32 v6, v36
+; CHECK-NEXT:    v_mov_b32_e32 v7, v37
+; CHECK-NEXT:    v_mov_b32_e32 v8, v38
+; CHECK-NEXT:    v_mov_b32_e32 v9, v39
+; CHECK-NEXT:    v_mov_b32_e32 v10, v40
+; CHECK-NEXT:    v_mov_b32_e32 v11, v41
+; CHECK-NEXT:    v_mov_b32_e32 v12, v42
+; CHECK-NEXT:    v_mov_b32_e32 v13, v43
+; CHECK-NEXT:    v_mov_b32_e32 v14, v44
+; CHECK-NEXT:    v_mov_b32_e32 v15, v45
+; CHECK-NEXT:    v_mov_b32_e32 v16, v46
+; CHECK-NEXT:    v_mov_b32_e32 v17, v47
+; CHECK-NEXT:    v_mov_b32_e32 v18, v48
+; CHECK-NEXT:    v_mov_b32_e32 v19, v49
+; CHECK-NEXT:    v_mov_b32_e32 v20, v50
+; CHECK-NEXT:    v_mov_b32_e32 v21, v51
+; CHECK-NEXT:    v_mov_b32_e32 v22, v52
+; CHECK-NEXT:    v_mov_b32_e32 v23, v53
+; CHECK-NEXT:    v_mov_b32_e32 v24, v54
+; CHECK-NEXT:    v_mov_b32_e32 v25, v55
+; CHECK-NEXT:    v_mov_b32_e32 v26, v56
+; CHECK-NEXT:    v_mov_b32_e32 v27, v57
+; CHECK-NEXT:    v_mov_b32_e32 v28, v58
+; CHECK-NEXT:    v_mov_b32_e32 v29, v59
+; CHECK-NEXT:    v_mov_b32_e32 v30, v60
+; CHECK-NEXT:    v_mov_b32_e32 v31, v61
+; CHECK-NEXT:    v_mov_b32_e32 v32, 0
+; CHECK-NEXT:    s_nop 0
+; CHECK-NEXT:    v_mfma_f32_32x32x1_2b_f32 v[0:31], a0, a1, v[0:31]
 ; CHECK-NEXT:    s_nop 7
 ; CHECK-NEXT:    s_nop 7
 ; CHECK-NEXT:    s_nop 1
-; CHECK-NEXT:    global_store_dwordx4 v0, a[24:27], s[0:1] offset:96
-; CHECK-NEXT:    global_store_dwordx4 v0, a[28:31], s[0:1] offset:112
-; CHECK-NEXT:    global_store_dwordx4 v0, a[16:19], s[0:1] offset:64
-; CHECK-NEXT:    global_store_dwordx4 v0, a[20:23], s[0:1] offset:80
-; CHECK-NEXT:    global_store_dwordx4 v0, a[8:11], s[0:1] offset:32
-; CHECK-NEXT:    global_store_dwordx4 v0, a[12:15], s[0:1] offset:48
-; CHECK-NEXT:    global_store_dwordx4 v0, a[0:3], s[0:1]
-; CHECK-NEXT:    global_store_dwordx4 v0, a[4:7], s[0:1] offset:16
+; CHECK-NEXT:    global_store_dwordx4 v32, v[24:27], s[0:1] offset:96
+; CHECK-NEXT:    global_store_dwordx4 v32, v[28:31], s[0:1] offset:112
+; CHECK-NEXT:    global_store_dwordx4 v32, v[16:19], s[0:1] offset:64
+; CHECK-NEXT:    global_store_dwordx4 v32, v[20:23], s[0:1] offset:80
+; CHECK-NEXT:    global_store_dwordx4 v32, v[8:11], s[0:1] offset:32
+; CHECK-NEXT:    global_store_dwordx4 v32, v[12:15], s[0:1] offset:48
+; CHECK-NEXT:    global_store_dwordx4 v32, v[0:3], s[0:1]
+; CHECK-NEXT:    global_store_dwordx4 v32, v[4:7], s[0:1] offset:16
 ; CHECK-NEXT:    s_endpgm
 bb:
   %id = call i32 @llvm.amdgcn.workitem.id.x()
@@ -146,35 +90,36 @@ define amdgpu_kernel void @test_mfma_f32_32x32x1f32_rewrite_vgpr_mfma_noshuffle(
 ; CHECK-LABEL: test_mfma_f32_32x32x1f32_rewrite_vgpr_mfma_noshuffle:
 ; CHECK:       ; %bb.0: ; %bb
 ; CHECK-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; CHECK-NEXT:    v_and_b32_e32 v0, 0x3ff, v0
 ; CHECK-NEXT:    v_lshlrev_b32_e32 v0, 7, v0
-; CHECK-NEXT:    v_mov_b32_e32 v1, 2.0
+; CHECK-NEXT:    v_mov_b32_e32 v32, 1.0
+; CHECK-NEXT:    v_mov_b32_e32 v33, 2.0
 ; CHECK-NEXT:    s_waitcnt lgkmcnt(0)
-; CHECK-NEXT:    global_load_dwordx4 a[28:31], v0, s[0:1] offset:112
-; CHECK-NEXT:    global_load_dwordx4 a[24:27], v0, s[0:1] offset:96
-; CHECK-NEXT:    global_load_dwordx4 a[20:23], v0, s[0:1] offset:80
-; CHECK-NEXT:    global_load_dwordx4 a[16:19], v0, s[0:1] offset:64
-; CHECK-NEXT:    global_load_dwordx4 a[12:15], v0, s[0:1] offset:48
-; CHECK-NEXT:    global_load_dwordx4 a[8:11], v0, s[0:1] offset:32
-; CHECK-NEXT:    global_load_dwordx4 a[4:7], v0, s[0:1] offset:16
-; CHECK-NEXT:    global_load_dwordx4 a[0:3], v0, s[0:1]
-; CHECK-NEXT:    v_mov_b32_e32 v0, 1.0
-; CHECK-NEXT:    s_waitcnt vmcnt(0)
+; CHECK-NEXT:    global_load_dwordx4 v[28:31], v0, s[0:1] offset:112
+; CHECK-NEXT:    global_load_dwordx4 v[24:27], v0, s[0:1] offset:96
+; CHECK-NEXT:    global_load_dwordx4 v[20:23], v0, s[0:1] offset:80
+; CHECK-NEXT:    global_load_dwordx4 v[16:19], v0, s[0:1] offset:64
+; CHECK-NEXT:    global_load_dwordx4 v[12:15], v0, s[0:1] offset:48
+; CHECK-NEXT:    global_load_dwordx4 v[8:11], v0, s[0:1] offset:32
+; CHECK-NEXT:    global_load_dwordx4 v[4:7], v0, s[0:1] offset:16
 ; CHECK-NEXT:    s_nop 0
-; CHECK-NEXT:    v_mfma_f32_32x32x1f32 a[0:31], v0, v1, a[0:31]
-; CHECK-NEXT:    v_mfma_f32_32x32x1f32 a[0:31], v0, v1, a[0:31]
-; CHECK-NEXT:    v_mfma_f32_32x32x1f32 a[0:31], v0, v1, a[0:31]
-; CHECK-NEXT:    v_mov_b32_e32 v0, 0
+; CHECK-NEXT:    global_load_dwordx4 v[0:3], v0, s[0:1]
+; CHECK-NEXT:    s_waitcnt vmcnt(0)
+; CHECK-NEXT:    v_mfma_f32_32x32x1_2b_f32 v[0:31], v32, v33, v[0:31]
+; CHECK-NEXT:    v_mfma_f32_32x32x1_2b_f32 v[0:31], v32, v33, v[0:31]
+; CHECK-NEXT:    v_mfma_f32_32x32x1_2b_f32 v[0:31], v32, v33, v[0:31]
+; CHECK-NEXT:    v_mov_b32_e32 v32, 0
 ; CHECK-NEXT:    s_nop 7
 ; CHECK-NEXT:    s_nop 7
-; CHECK-NEXT:    s_nop 1
-; CHECK-NEXT:    global_store_dwordx4 v0, a[24:27], s[0:1] offset:96
-; CHECK-NEXT:    global_store_dwordx4 v0, a[28:31], s[0:1] offset:112
-; CHECK-NEXT:    global_store_dwordx4 v0, a[16:19], s[0:1] offset:64
-; CHECK-NEXT:    global_store_dwordx4 v0, a[20:23], s[0:1] offset:80
-; CHECK-NEXT:    global_store_dwordx4 v0, a[8:11], s[0:1] offset:32
-; CHECK-NEXT:    global_store_dwordx4 v0, a[12:15], s[0:1] offset:48
-; CHECK-NEXT:    global_store_dwordx4 v0, a[0:3], s[0:1]
-; CHECK-NEXT:    global_store_dwordx4 v0, a[4:7], s[0:1] offset:16
+; CHECK-NEXT:    s_nop 0
+; CHECK-NEXT:    global_store_dwordx4 v32, v[24:27], s[0:1] offset:96
+; CHECK-NEXT:    global_store_dwordx4 v32, v[28:31], s[0:1] offset:112
+; CHECK-NEXT:    global_store_dwordx4 v32, v[16:19], s[0:1] offset:64
+; CHECK-NEXT:    global_store_dwordx4 v32, v[20:23], s[0:1] offset:80
+; CHECK-NEXT:    global_store_dwordx4 v32, v[8:11], s[0:1] offset:32
+; CHECK-NEXT:    global_store_dwordx4 v32, v[12:15], s[0:1] offset:48
+; CHECK-NEXT:    global_store_dwordx4 v32, v[0:3], s[0:1]
+; CHECK-NEXT:    global_store_dwordx4 v32, v[4:7], s[0:1] offset:16
 ; CHECK-NEXT:    s_endpgm
 bb:
   %id = call i32 @llvm.amdgcn.workitem.id.x()
@@ -187,9 +132,77 @@ bb:
   ret void
 }
 
+define amdgpu_kernel void @test_mfma_f32_32x32x1f32_rewrite_vgpr_mfma_imm0_src2(ptr addrspace(1) %arg) #0 {
+; CHECK-LABEL: test_mfma_f32_32x32x1f32_rewrite_vgpr_mfma_imm0_src2:
+; CHECK:       ; %bb.0: ; %bb
+; CHECK-NEXT:    v_mov_b32_e32 v32, 1.0
+; CHECK-NEXT:    v_mov_b32_e32 v33, 2.0
+; CHECK-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; CHECK-NEXT:    s_nop 0
+; CHECK-NEXT:    v_mfma_f32_32x32x1_2b_f32 v[0:31], v32, v33, 0
+; CHECK-NEXT:    v_mfma_f32_32x32x1_2b_f32 v[0:31], v32, v33, v[0:31]
+; CHECK-NEXT:    v_mfma_f32_32x32x1_2b_f32 v[0:31], v32, v33, v[0:31]
+; CHECK-NEXT:    v_mov_b32_e32 v32, 0
+; CHECK-NEXT:    s_waitcnt lgkmcnt(0)
+; CHECK-NEXT:    s_nop 7
+; CHECK-NEXT:    s_nop 7
+; CHECK-NEXT:    global_store_dwordx4 v32, v[28:31], s[0:1] offset:112
+; CHECK-NEXT:    global_store_dwordx4 v32, v[24:27], s[0:1] offset:96
+; CHECK-NEXT:    global_store_dwordx4 v32, v[20:23], s[0:1] offset:80
+; CHECK-NEXT:    global_store_dwordx4 v32, v[16:19], s[0:1] offset:64
+; CHECK-NEXT:    global_store_dwordx4 v32, v[12:15], s[0:1] offset:48
+; CHECK-NEXT:    global_store_dwordx4 v32, v[8:11], s[0:1] offset:32
+; CHECK-NEXT:    global_store_dwordx4 v32, v[4:7], s[0:1] offset:16
+; CHECK-NEXT:    global_store_dwordx4 v32, v[0:3], s[0:1]
+; CHECK-NEXT:    s_endpgm
+bb:
+  %id = call i32 @llvm.amdgcn.workitem.id.x()
+  %gep = getelementptr <32 x float>, ptr addrspace(1) %arg, i32 %id
+  %in.1 = load <32 x float>, ptr addrspace(1) %gep, align 128
+  %mai.1 = call <32 x float> @llvm.amdgcn.mfma.f32.32x32x1f32(float 1.0, float 2.0, <32 x float> zeroinitializer, i32 0, i32 0, i32 0)
+  %mai.2 = call <32 x float> @llvm.amdgcn.mfma.f32.32x32x1f32(float 1.0, float 2.0, <32 x float> %mai.1, i32 0, i32 0, i32 0)
+  %mai.3 = call <32 x float> @llvm.amdgcn.mfma.f32.32x32x1f32(float 1.0, float 2.0, <32 x float> %mai.2, i32 0, i32 0, i32 0)
+  store <32 x float> %mai.3, ptr addrspace(1) %arg, align 128
+  ret void
+}
+
+define amdgpu_kernel void @test_mfma_f32_32x32x1f32_rewrite_vgpr_mfma_imm1_src2(ptr addrspace(1) %arg) #0 {
+; CHECK-LABEL: test_mfma_f32_32x32x1f32_rewrite_vgpr_mfma_imm1_src2:
+; CHECK:       ; %bb.0: ; %bb
+; CHECK-NEXT:    v_mov_b32_e32 v32, 1.0
+; CHECK-NEXT:    v_mov_b32_e32 v33, 2.0
+; CHECK-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; CHECK-NEXT:    s_nop 0
+; CHECK-NEXT:    v_mfma_f32_32x32x1_2b_f32 v[0:31], v32, v33, 1.0
+; CHECK-NEXT:    v_mfma_f32_32x32x1_2b_f32 v[0:31], v32, v33, v[0:31]
+; CHECK-NEXT:    v_mfma_f32_32x32x1_2b_f32 v[0:31], v32, v33, v[0:31]
+; CHECK-NEXT:    v_mov_b32_e32 v32, 0
+; CHECK-NEXT:    s_waitcnt lgkmcnt(0)
+; CHECK-NEXT:    s_nop 7
+; CHECK-NEXT:    s_nop 7
+; CHECK-NEXT:    global_store_dwordx4 v32, v[28:31], s[0:1] offset:112
+; CHECK-NEXT:    global_store_dwordx4 v32, v[24:27], s[0:1] offset:96
+; CHECK-NEXT:    global_store_dwordx4 v32, v[20:23], s[0:1] offset:80
+; CHECK-NEXT:    global_store_dwordx4 v32, v[16:19], s[0:1] offset:64
+; CHECK-NEXT:    global_store_dwordx4 v32, v[12:15], s[0:1] offset:48
+; CHECK-NEXT:    global_store_dwordx4 v32, v[8:11], s[0:1] offset:32
+; CHECK-NEXT:    global_store_dwordx4 v32, v[4:7], s[0:1] offset:16
+; CHECK-NEXT:    global_store_dwordx4 v32, v[0:3], s[0:1]
+; CHECK-NEXT:    s_endpgm
+bb:
+  %id = call i32 @llvm.amdgcn.workitem.id.x()
+  %gep = getelementptr <32 x float>, ptr addrspace(1) %arg, i32 %id
+  %in.1 = load <32 x float>, ptr addrspace(1) %gep, align 128
+  %mai.1 = call <32 x float> @llvm.amdgcn.mfma.f32.32x32x1f32(float 1.0, float 2.0, <32 x float> splat (float 1.0), i32 0, i32 0, i32 0)
+  %mai.2 = call <32 x float> @llvm.amdgcn.mfma.f32.32x32x1f32(float 1.0, float 2.0, <32 x float> %mai.1, i32 0, i32 0, i32 0)
+  %mai.3 = call <32 x float> @llvm.amdgcn.mfma.f32.32x32x1f32(float 1.0, float 2.0, <32 x float> %mai.2, i32 0, i32 0, i32 0)
+  store <32 x float> %mai.3, ptr addrspace(1) %arg, align 128
+  ret void
+}
+
 declare <32 x float> @llvm.amdgcn.mfma.f32.32x32x1f32(float, float, <32 x float>, i32 immarg, i32 immarg, i32 immarg) #1
 declare noundef i32 @llvm.amdgcn.workitem.id.x() #2
 
-attributes #0 = { "amdgpu-flat-work-group-size"="1,256" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "amdgpu-waves-per-eu"="4,4" }
+attributes #0 = { nounwind "amdgpu-flat-work-group-size"="1,256" "amdgpu-waves-per-eu"="4,4" }
 attributes #1 = { convergent nocallback nofree nosync nounwind willreturn memory(none) }
 attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }