Skip to content

Commit ac17b50

Browse files
topperctopperc
committed
[RISCV] Use getSignedTargetConstant. NFC
1 parent 1d0b285 commit ac17b50

File tree

5 files changed

+61
-66
lines changed

5 files changed

+61
-66
lines changed

‎llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp‎

Lines changed: 44 additions & 48 deletions
Original file line numberDiff line numberDiff line change
@@ -176,8 +176,7 @@ static SDValue selectImmSeq(SelectionDAG *CurDAG, const SDLoc &DL, const MVT VT,
176176
RISCVMatInt::InstSeq &Seq) {
177177
SDValue SrcReg = CurDAG->getRegister(RISCV::X0, VT);
178178
for (const RISCVMatInt::Inst &Inst : Seq) {
179-
SDValue SDImm =
180-
CurDAG->getSignedConstant(Inst.getImm(), DL, VT, /*isTarget=*/true);
179+
SDValue SDImm = CurDAG->getSignedTargetConstant(Inst.getImm(), DL, VT);
181180
SDNode *Result = nullptr;
182181
switch (Inst.getOpndKind()) {
183182
case RISCVMatInt::Imm:
@@ -208,10 +207,10 @@ static SDValue selectImm(SelectionDAG *CurDAG, const SDLoc &DL, const MVT VT,
208207

209208
// Use a rematerializable pseudo instruction for short sequences if enabled.
210209
if (Seq.size() == 2 && UsePseudoMovImm)
211-
return SDValue(CurDAG->getMachineNode(RISCV::PseudoMovImm, DL, VT,
212-
CurDAG->getSignedConstant(
213-
Imm, DL, VT, /*isTarget=*/true)),
214-
0);
210+
return SDValue(
211+
CurDAG->getMachineNode(RISCV::PseudoMovImm, DL, VT,
212+
CurDAG->getSignedTargetConstant(Imm, DL, VT)),
213+
0);
215214

216215
// See if we can create this constant as (ADD (SLLI X, C), X) where X is at
217216
// worst an LUI+ADDIW. This will require an extra register, but avoids a
@@ -594,7 +593,7 @@ bool RISCVDAGToDAGISel::tryShrinkShlLogicImm(SDNode *Node) {
594593

595594
SDNode *BinOp = CurDAG->getMachineNode(
596595
BinOpc, DL, VT, Shift.getOperand(0),
597-
CurDAG->getSignedConstant(ShiftedVal, DL, VT, /*isTarget=*/true));
596+
CurDAG->getSignedTargetConstant(ShiftedVal, DL, VT));
598597
SDNode *SLLI =
599598
CurDAG->getMachineNode(ShOpc, DL, VT, SDValue(BinOp, 0),
600599
CurDAG->getTargetConstant(ShAmt, DL, VT));
@@ -723,11 +722,10 @@ bool RISCVDAGToDAGISel::tryIndexedLoad(SDNode *Node) {
723722
return false;
724723

725724
EVT Ty = Ld->getOffset().getValueType();
726-
SDValue Ops[] = {Ld->getBasePtr(),
727-
CurDAG->getSignedConstant(Offset >> Shift, SDLoc(Node), Ty,
728-
/*isTarget=*/true),
729-
CurDAG->getTargetConstant(Shift, SDLoc(Node), Ty),
730-
Ld->getChain()};
725+
SDValue Ops[] = {
726+
Ld->getBasePtr(),
727+
CurDAG->getSignedTargetConstant(Offset >> Shift, SDLoc(Node), Ty),
728+
CurDAG->getTargetConstant(Shift, SDLoc(Node), Ty), Ld->getChain()};
731729
SDNode *New = CurDAG->getMachineNode(Opcode, SDLoc(Node), Ld->getValueType(0),
732730
Ld->getValueType(1), MVT::Other, Ops);
733731

@@ -2515,8 +2513,8 @@ bool RISCVDAGToDAGISel::SelectFrameAddrRegImm(SDValue Addr, SDValue &Base,
25152513
if (isInt<12>(CVal)) {
25162514
Base = CurDAG->getTargetFrameIndex(FIN->getIndex(),
25172515
Subtarget->getXLenVT());
2518-
Offset = CurDAG->getSignedConstant(
2519-
CVal, SDLoc(Addr), Subtarget->getXLenVT(), /*isTarget=*/true);
2516+
Offset = CurDAG->getSignedTargetConstant(CVal, SDLoc(Addr),
2517+
Subtarget->getXLenVT());
25202518
return true;
25212519
}
25222520
}
@@ -2555,7 +2553,7 @@ static bool selectConstantAddr(SelectionDAG *CurDAG, const SDLoc &DL,
25552553
} else {
25562554
Base = CurDAG->getRegister(RISCV::X0, VT);
25572555
}
2558-
Offset = CurDAG->getSignedConstant(Lo12, DL, VT, /*isTarget=*/true);
2556+
Offset = CurDAG->getSignedTargetConstant(Lo12, DL, VT);
25592557
return true;
25602558
}
25612559

@@ -2577,7 +2575,7 @@ static bool selectConstantAddr(SelectionDAG *CurDAG, const SDLoc &DL,
25772575
assert(!Seq.empty() && "Expected more instructions in sequence");
25782576

25792577
Base = selectImmSeq(CurDAG, DL, VT, Seq);
2580-
Offset = CurDAG->getSignedConstant(Lo12, DL, VT, /*isTarget=*/true);
2578+
Offset = CurDAG->getSignedTargetConstant(Lo12, DL, VT);
25812579
return true;
25822580
}
25832581

@@ -2727,7 +2725,7 @@ bool RISCVDAGToDAGISel::SelectAddrRegImm(SDValue Addr, SDValue &Base,
27272725

27282726
if (auto *FIN = dyn_cast<FrameIndexSDNode>(Base))
27292727
Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), VT);
2730-
Offset = CurDAG->getSignedConstant(CVal, DL, VT, /*isTarget=*/true);
2728+
Offset = CurDAG->getSignedTargetConstant(CVal, DL, VT);
27312729
return true;
27322730
}
27332731
}
@@ -2744,11 +2742,10 @@ bool RISCVDAGToDAGISel::SelectAddrRegImm(SDValue Addr, SDValue &Base,
27442742
if (CVal >= -4096 && CVal <= (4094 - RV32ZdinxRange)) {
27452743
int64_t Adj = CVal < 0 ? -2048 : 2047;
27462744
Base = SDValue(
2747-
CurDAG->getMachineNode(
2748-
RISCV::ADDI, DL, VT, Addr.getOperand(0),
2749-
CurDAG->getSignedConstant(Adj, DL, VT, /*isTarget=*/true)),
2745+
CurDAG->getMachineNode(RISCV::ADDI, DL, VT, Addr.getOperand(0),
2746+
CurDAG->getSignedTargetConstant(Adj, DL, VT)),
27502747
0);
2751-
Offset = CurDAG->getSignedConstant(CVal - Adj, DL, VT, /*isTarget=*/true);
2748+
Offset = CurDAG->getSignedTargetConstant(CVal - Adj, DL, VT);
27522749
return true;
27532750
}
27542751

@@ -2802,7 +2799,7 @@ bool RISCVDAGToDAGISel::SelectAddrRegImmLsb00000(SDValue Addr, SDValue &Base,
28022799

28032800
if (auto *FIN = dyn_cast<FrameIndexSDNode>(Base))
28042801
Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), VT);
2805-
Offset = CurDAG->getSignedConstant(CVal, DL, VT, /*isTarget=*/true);
2802+
Offset = CurDAG->getSignedTargetConstant(CVal, DL, VT);
28062803
return true;
28072804
}
28082805
}
@@ -2818,12 +2815,12 @@ bool RISCVDAGToDAGISel::SelectAddrRegImmLsb00000(SDValue Addr, SDValue &Base,
28182815
if ((-2049 >= CVal && CVal >= -4096) || (4065 >= CVal && CVal >= 2017)) {
28192816
int64_t Adj = CVal < 0 ? -2048 : 2016;
28202817
int64_t AdjustedOffset = CVal - Adj;
2821-
Base = SDValue(CurDAG->getMachineNode(
2822-
RISCV::ADDI, DL, VT, Addr.getOperand(0),
2823-
CurDAG->getSignedConstant(AdjustedOffset, DL, VT,
2824-
/*isTarget=*/true)),
2825-
0);
2826-
Offset = CurDAG->getSignedConstant(Adj, DL, VT, /*isTarget=*/true);
2818+
Base =
2819+
SDValue(CurDAG->getMachineNode(
2820+
RISCV::ADDI, DL, VT, Addr.getOperand(0),
2821+
CurDAG->getSignedTargetConstant(AdjustedOffset, DL, VT)),
2822+
0);
2823+
Offset = CurDAG->getSignedTargetConstant(Adj, DL, VT);
28272824
return true;
28282825
}
28292826

@@ -2969,21 +2966,21 @@ bool RISCVDAGToDAGISel::selectSETCC(SDValue N, ISD::CondCode ExpectedCCVal,
29692966
// If the RHS is -2048, we can use xori to produce 0 if the LHS is -2048 and
29702967
// non-zero otherwise.
29712968
if (CVal == -2048) {
2972-
Val = SDValue(CurDAG->getMachineNode(
2973-
RISCV::XORI, DL, N->getValueType(0), LHS,
2974-
CurDAG->getSignedConstant(CVal, DL, N->getValueType(0),
2975-
/*isTarget=*/true)),
2976-
0);
2969+
Val = SDValue(
2970+
CurDAG->getMachineNode(
2971+
RISCV::XORI, DL, N->getValueType(0), LHS,
2972+
CurDAG->getSignedTargetConstant(CVal, DL, N->getValueType(0))),
2973+
0);
29772974
return true;
29782975
}
29792976
// If the RHS is [-2047,2048], we can use addi with -RHS to produce 0 if the
29802977
// LHS is equal to the RHS and non-zero otherwise.
29812978
if (isInt<12>(CVal) || CVal == 2048) {
2982-
Val = SDValue(CurDAG->getMachineNode(
2983-
RISCV::ADDI, DL, N->getValueType(0), LHS,
2984-
CurDAG->getSignedConstant(-CVal, DL, N->getValueType(0),
2985-
/*isTarget=*/true)),
2986-
0);
2979+
Val = SDValue(
2980+
CurDAG->getMachineNode(
2981+
RISCV::ADDI, DL, N->getValueType(0), LHS,
2982+
CurDAG->getSignedTargetConstant(-CVal, DL, N->getValueType(0))),
2983+
0);
29872984
return true;
29882985
}
29892986
if (isPowerOf2_64(CVal) && Subtarget->hasStdExtZbs()) {
@@ -3424,8 +3421,7 @@ bool RISCVDAGToDAGISel::selectSimm5Shl2(SDValue N, SDValue &Simm5,
34243421
return false;
34253422

34263423
EVT Ty = N->getValueType(0);
3427-
Simm5 = CurDAG->getSignedConstant(Offset >> Shift, SDLoc(N), Ty,
3428-
/*isTarget=*/true);
3424+
Simm5 = CurDAG->getSignedTargetConstant(Offset >> Shift, SDLoc(N), Ty);
34293425
Shl2 = CurDAG->getTargetConstant(Shift, SDLoc(N), Ty);
34303426
return true;
34313427
}
@@ -3442,16 +3438,16 @@ bool RISCVDAGToDAGISel::selectVLOp(SDValue N, SDValue &VL) {
34423438
N->getValueType(0));
34433439
} else if (C && C->isAllOnes()) {
34443440
// Treat all ones as VLMax.
3445-
VL = CurDAG->getSignedConstant(RISCV::VLMaxSentinel, SDLoc(N),
3446-
N->getValueType(0), /*isTarget=*/true);
3441+
VL = CurDAG->getSignedTargetConstant(RISCV::VLMaxSentinel, SDLoc(N),
3442+
N->getValueType(0));
34473443
} else if (isa<RegisterSDNode>(N) &&
34483444
cast<RegisterSDNode>(N)->getReg() == RISCV::X0) {
34493445
// All our VL operands use an operand that allows GPRNoX0 or an immediate
34503446
// as the register class. Convert X0 to a special immediate to pass the
34513447
// MachineVerifier. This is recognized specially by the vsetvli insertion
34523448
// pass.
3453-
VL = CurDAG->getSignedConstant(RISCV::VLMaxSentinel, SDLoc(N),
3454-
N->getValueType(0), /*isTarget=*/true);
3449+
VL = CurDAG->getSignedTargetConstant(RISCV::VLMaxSentinel, SDLoc(N),
3450+
N->getValueType(0));
34553451
} else {
34563452
VL = N;
34573453
}
@@ -3509,8 +3505,8 @@ static bool selectVSplatImmHelper(SDValue N, SDValue &SplatVal,
35093505
if (!ValidateImm(SplatImm))
35103506
return false;
35113507

3512-
SplatVal = DAG.getSignedConstant(SplatImm, SDLoc(N), Subtarget.getXLenVT(),
3513-
/*isTarget=*/true);
3508+
SplatVal =
3509+
DAG.getSignedTargetConstant(SplatImm, SDLoc(N), Subtarget.getXLenVT());
35143510
return true;
35153511
}
35163512

@@ -3610,8 +3606,8 @@ bool RISCVDAGToDAGISel::selectRVVSimm5(SDValue N, unsigned Width,
36103606
if (!isInt<5>(ImmVal))
36113607
return false;
36123608

3613-
Imm = CurDAG->getSignedConstant(ImmVal, SDLoc(N), Subtarget->getXLenVT(),
3614-
/*isTarget=*/true);
3609+
Imm = CurDAG->getSignedTargetConstant(ImmVal, SDLoc(N),
3610+
Subtarget->getXLenVT());
36153611
return true;
36163612
}
36173613

‎llvm/lib/Target/RISCV/RISCVISelLowering.cpp‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -20784,8 +20784,8 @@ void RISCVTargetLowering::LowerAsmOperandForConstraint(
2078420784
if (auto *C = dyn_cast<ConstantSDNode>(Op)) {
2078520785
uint64_t CVal = C->getSExtValue();
2078620786
if (isInt<12>(CVal))
20787-
Ops.push_back(DAG.getSignedConstant(
20788-
CVal, SDLoc(Op), Subtarget.getXLenVT(), /*isTarget=*/true));
20787+
Ops.push_back(DAG.getSignedTargetConstant(CVal, SDLoc(Op),
20788+
Subtarget.getXLenVT()));
2078920789
}
2079020790
return;
2079120791
case 'J':

‎llvm/lib/Target/RISCV/RISCVInstrInfo.td‎

Lines changed: 7 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -415,14 +415,14 @@ def AddrRegImm : ComplexPattern<iPTR, 2, "SelectAddrRegImm">;
415415

416416
// Return the negation of an immediate value.
417417
def NegImm : SDNodeXForm<imm, [{
418-
return CurDAG->getSignedConstant(-N->getSExtValue(), SDLoc(N),
419-
N->getValueType(0), /*isTarget=*/true);
418+
return CurDAG->getSignedTargetConstant(-N->getSExtValue(), SDLoc(N),
419+
N->getValueType(0));
420420
}]>;
421421

422422
// Return an immediate value minus 32.
423423
def ImmSub32 : SDNodeXForm<imm, [{
424-
return CurDAG->getSignedConstant(N->getSExtValue() - 32, SDLoc(N),
425-
N->getValueType(0), /*isTarget=*/true);
424+
return CurDAG->getSignedTargetConstant(N->getSExtValue() - 32, SDLoc(N),
425+
N->getValueType(0));
426426
}]>;
427427

428428
// Return an immediate subtracted from XLen.
@@ -454,16 +454,15 @@ def AddiPair : PatLeaf<(imm), [{
454454
def AddiPairImmSmall : SDNodeXForm<imm, [{
455455
int64_t Imm = N->getSExtValue();
456456
int64_t Adj = N->getSExtValue() < 0 ? -2048 : 2047;
457-
return CurDAG->getSignedConstant(Imm - Adj, SDLoc(N),
458-
N->getValueType(0), /*isTarget=*/true);
457+
return CurDAG->getSignedTargetConstant(Imm - Adj, SDLoc(N),
458+
N->getValueType(0));
459459
}]>;
460460

461461
// Return -2048 if immediate is negative or 2047 if positive. These are the
462462
// largest simm12 values.
463463
def AddiPairImmLarge : SDNodeXForm<imm, [{
464464
int64_t Imm = N->getSExtValue() < 0 ? -2048 : 2047;
465-
return CurDAG->getSignedConstant(Imm, SDLoc(N),
466-
N->getValueType(0), /*isTarget=*/true);
465+
return CurDAG->getSignedTargetConstant(Imm, SDLoc(N), N->getValueType(0));
467466
}]>;
468467

469468
def TrailingZeros : SDNodeXForm<imm, [{

‎llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -104,8 +104,8 @@ def vec_rm : RISCVOp {
104104
def VLOp : ComplexPattern<XLenVT, 1, "selectVLOp">;
105105

106106
def DecImm : SDNodeXForm<imm, [{
107-
return CurDAG->getSignedConstant(N->getSExtValue() - 1, SDLoc(N),
108-
N->getValueType(0), /*isTarget=*/true);
107+
return CurDAG->getSignedTargetConstant(N->getSExtValue() - 1, SDLoc(N),
108+
N->getValueType(0));
109109
}]>;
110110

111111
defvar TAIL_AGNOSTIC = 1;

‎llvm/lib/Target/RISCV/RISCVInstrInfoZb.td‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -145,8 +145,8 @@ def BCLRIANDIMask : PatLeaf<(imm), [{
145145
}]>;
146146

147147
def BCLRIANDIMaskLow : SDNodeXForm<imm, [{
148-
return CurDAG->getSignedConstant((N->getZExtValue() & 0x7ff) | ~0x7ffull,
149-
SDLoc(N), N->getValueType(0), /*isTarget=*/true);
148+
return CurDAG->getSignedTargetConstant((N->getZExtValue() & 0x7ff) | ~0x7ffull,
149+
SDLoc(N), N->getValueType(0));
150150
}]>;
151151

152152
def CSImm12MulBy4 : PatLeaf<(imm), [{
@@ -167,13 +167,13 @@ def CSImm12MulBy8 : PatLeaf<(imm), [{
167167
}]>;
168168

169169
def SimmShiftRightBy2XForm : SDNodeXForm<imm, [{
170-
return CurDAG->getSignedConstant(N->getSExtValue() >> 2, SDLoc(N),
171-
N->getValueType(0), /*isTarget=*/true);
170+
return CurDAG->getSignedTargetConstant(N->getSExtValue() >> 2, SDLoc(N),
171+
N->getValueType(0));
172172
}]>;
173173

174174
def SimmShiftRightBy3XForm : SDNodeXForm<imm, [{
175-
return CurDAG->getSignedConstant(N->getSExtValue() >> 3, SDLoc(N),
176-
N->getValueType(0), /*isTarget=*/true);
175+
return CurDAG->getSignedTargetConstant(N->getSExtValue() >> 3, SDLoc(N),
176+
N->getValueType(0));
177177
}]>;
178178

179179
// Pattern to exclude simm12 immediates from matching, namely `non_imm12`.

0 commit comments

Comments
 (0)