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SystemZ: Regenerate baseline checks for some coalescer tests (llvm#118322)
These were missing -NEXT checks and also had some dead checks. Also switch a test to actually check the output.
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-119
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-119
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‎llvm/test/CodeGen/SystemZ/regcoal-subranges-update-remat.mir‎

Lines changed: 4 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -29,13 +29,12 @@ tracksRegLiveness: true
2929
body: |
3030
bb.0:
3131
32-
; CHECK-LABEL
3332
; CHECK-LABEL: name: main
3433
; CHECK: [[LGHI:%[0-9]+]]:gr64bit = LGHI 25
35-
; CHECK: CHIMux [[LGHI]].subreg_l32, 0, implicit-def $cc
36-
; CHECK: [[LGHI1:%[0-9]+]]:gr64bit = LGHI 25
37-
; CHECK: undef [[LGHI1]].subreg_l32:gr64bit = MSFI [[LGHI1]].subreg_l32, -117440512
38-
; CHECK: Return implicit [[LGHI1]].subreg_l32
34+
; CHECK-NEXT: CHIMux [[LGHI]].subreg_l32, 0, implicit-def $cc
35+
; CHECK-NEXT: [[LGHI1:%[0-9]+]]:gr64bit = LGHI 25
36+
; CHECK-NEXT: undef [[LGHI1:%[0-9]+]].subreg_l32:gr64bit = MSFI [[LGHI1]].subreg_l32, -117440512
37+
; CHECK-NEXT: Return implicit [[LGHI1]].subreg_l32
3938
%0:gr64bit = LGHI 25
4039
%1:gr32bit = COPY %0.subreg_l32
4140
%1:gr32bit = MSFI %1, -117440512

‎llvm/test/CodeGen/SystemZ/regcoal-subranges-update.mir‎

Lines changed: 23 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -25,12 +25,12 @@ body: |
2525
2626
; CHECK-LABEL: name: main
2727
; CHECK: [[LGHI:%[0-9]+]]:gr64bit = LGHI 43
28-
; CHECK: [[LGHI1:%[0-9]+]]:gr64bit = LGHI 43
29-
; CHECK: [[LGHI1]].subreg_l32:gr64bit = MSR [[LGHI1]].subreg_l32, [[LGHI1]].subreg_l32
30-
; CHECK: [[LGHI1]].subreg_l32:gr64bit = AHIMux [[LGHI1]].subreg_l32, 9, implicit-def dead $cc
31-
; CHECK: undef %3.subreg_l64:gr128bit = LGFI -245143785, implicit [[LGHI1]].subreg_l32
32-
; CHECK: [[DLGR:%[0-9]+]]:gr128bit = DLGR [[DLGR]], [[LGHI]]
33-
; CHECK: Return implicit [[DLGR]]
28+
; CHECK-NEXT: [[LGHI1:%[0-9]+]]:gr64bit = LGHI 43
29+
; CHECK-NEXT: undef [[LGHI1:%[0-9]+]].subreg_l32:gr64bit = MSR [[LGHI1]].subreg_l32, [[LGHI1]].subreg_l32
30+
; CHECK-NEXT: [[LGHI1:%[0-9]+]].subreg_l32:gr64bit = AHIMux [[LGHI1]].subreg_l32, 9, implicit-def dead $cc
31+
; CHECK-NEXT: undef [[LGFI:%[0-9]+]].subreg_l64:gr128bit = LGFI -245143785, implicit [[LGHI1]].subreg_l32
32+
; CHECK-NEXT: [[LGFI:%[0-9]+]]:gr128bit = DLGR [[LGFI]], [[LGHI]]
33+
; CHECK-NEXT: Return implicit [[LGFI]]
3434
%0:gr64bit = LGHI 43
3535
%1:gr32bit = COPY %0.subreg_l32
3636
%1:gr32bit = MSR %1, %1
@@ -55,20 +55,23 @@ liveins: []
5555
body: |
5656
; CHECK-LABEL: name: segfault
5757
; CHECK: bb.0:
58-
; CHECK: successors: %bb.1(0x80000000)
59-
; CHECK: [[LGHI:%[0-9]+]]:addr64bit = LGHI 0
60-
; CHECK: bb.1:
61-
; CHECK: successors: %bb.1(0x80000000)
62-
; CHECK: ADJCALLSTACKDOWN 0, 0
63-
; CHECK: [[LGFR:%[0-9]+]]:gr64bit = LGFR [[LGHI]].subreg_l32
64-
; CHECK: $r2d = LGHI 123
65-
; CHECK: $r3d = LGHI 0
66-
; CHECK: $r4d = LGHI 0
67-
; CHECK: $r5d = COPY [[LGFR]]
68-
; CHECK: KILL killed $r2d, killed $r3d, killed $r4d, $r5d, csr_systemz_elf, implicit-def dead $r14d, implicit-def dead $cc
69-
; CHECK: ADJCALLSTACKUP 0, 0
70-
; CHECK: [[LGHI]]:addr64bit = nuw nsw LA [[LGHI]], 1, $noreg
71-
; CHECK: J %bb.1
58+
; CHECK-NEXT: successors: %bb.1(0x80000000)
59+
; CHECK-NEXT: {{ $}}
60+
; CHECK-NEXT: [[LGHI:%[0-9]+]]:addr64bit = LGHI 0
61+
; CHECK-NEXT: {{ $}}
62+
; CHECK-NEXT: bb.1:
63+
; CHECK-NEXT: successors: %bb.1(0x80000000)
64+
; CHECK-NEXT: {{ $}}
65+
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0
66+
; CHECK-NEXT: [[LGFR:%[0-9]+]]:gr64bit = LGFR [[LGHI]].subreg_l32
67+
; CHECK-NEXT: $r2d = LGHI 123
68+
; CHECK-NEXT: $r3d = LGHI 0
69+
; CHECK-NEXT: $r4d = LGHI 0
70+
; CHECK-NEXT: $r5d = COPY [[LGFR]]
71+
; CHECK-NEXT: KILL killed $r2d, killed $r3d, killed $r4d, $r5d, csr_systemz_elf, implicit-def dead $r14d, implicit-def dead $cc
72+
; CHECK-NEXT: ADJCALLSTACKUP 0, 0
73+
; CHECK-NEXT: [[LGHI:%[0-9]+]]:addr64bit = nuw nsw LA [[LGHI]], 1, $noreg
74+
; CHECK-NEXT: J %bb.1
7275
bb.0:
7376
successors: %bb.1(0x80000000)
7477

‎llvm/test/CodeGen/SystemZ/regcoal-undef-lane-4-rm-cp-commuting-def.mir‎

Lines changed: 57 additions & 43 deletions
Original file line numberDiff line numberDiff line change
@@ -15,56 +15,70 @@
1515
# only partial defined before being fully copied.
1616
#
1717
# PR40215.
18+
19+
20+
# The coalescer should have been able to swap the operands of
21+
# the OR, hence eliminating the copy of %20 and %18.
22+
# This is also visible here because the ROSBG operand was LHS
23+
# before the coalescer, now it is RHS.
1824
---
1925
name: main
2026
alignment: 16
2127
tracksRegLiveness: true
22-
machineFunctionInfo: {}
2328
body: |
2429
; CHECK-LABEL: name: main
2530
; CHECK: bb.0:
26-
; CHECK: successors: %bb.1(0x80000000)
27-
; CHECK: [[LGHI:%[0-9]+]]:addr64bit = LGHI -30
28-
; CHECK: [[LHIMux:%[0-9]+]]:grx32bit = LHIMux 1
29-
; CHECK: [[LHIMux1:%[0-9]+]]:grx32bit = LHIMux 0
30-
; CHECK: undef %20.subreg_l32:gr64bit = IMPLICIT_DEF
31-
; CHECK: bb.1:
32-
; CHECK: successors: %bb.3(0x00000001), %bb.4(0x7fffffff)
33-
; CHECK: CHIMux [[LHIMux]], 0, implicit-def $cc
34-
; CHECK: BRC 14, 6, %bb.3, implicit killed $cc
35-
; CHECK: J %bb.4
36-
; CHECK: bb.2:
37-
; CHECK: successors:
38-
; CHECK: STMux %20.subreg_l32, undef %8:addr64bit, 0, $noreg :: (store (s32) into `ptr undef`)
39-
; CHECK: bb.3:
40-
; CHECK: successors:
41-
; CHECK: bb.4:
42-
; CHECK: successors: %bb.5(0x30000000), %bb.6(0x50000000)
43-
; CHECK: [[LAY:%[0-9]+]]:gr64bit = LAY [[LGHI]], 19838, $noreg
44-
; CHECK: [[LAY1:%[0-9]+]]:gr64bit = LAY [[LGHI]], 19840, $noreg
45-
; CHECK: [[LAY2:%[0-9]+]]:gr64bit = LAY [[LGHI]], 19844, $noreg
46-
; CHECK: [[OGR:%[0-9]+]]:gr64bit = OGR [[OGR]], [[LAY]], implicit-def dead $cc
47-
; CHECK: undef %19.subreg_l32:gr64bit = AHIMuxK [[LGHI]].subreg_l32, 19843, implicit-def dead $cc
48-
; CHECK: [[ROSBG:%[0-9]+]]:gr64bit = ROSBG [[ROSBG]], [[OGR]], 32, 63, 0, implicit-def dead $cc
49-
; The coalescer should have been able to swap the operands of
50-
; the OR, hence eliminating the copy of %20 and %18.
51-
; This is also visible here because the ROSBG operand was LHS
52-
; before the coalescer, now it is RHS.
53-
; CHECK: %20.subreg_l32:gr64bit = OR %20.subreg_l32, [[ROSBG]].subreg_l32, implicit-def dead $cc
54-
; CHECK: [[ROSBG1:%[0-9]+]]:gr64bit = ROSBG [[ROSBG1]], [[LAY1]], 32, 63, 0, implicit-def dead $cc
55-
; CHECK: CHIMux [[LHIMux1]], 0, implicit-def $cc
56-
; CHECK: BRC 14, 6, %bb.6, implicit killed $cc
57-
; CHECK: J %bb.5
58-
; CHECK: bb.5:
59-
; CHECK: successors: %bb.6(0x80000000)
60-
; CHECK: bb.6:
61-
; CHECK: successors: %bb.2(0x00000001), %bb.7(0x7fffffff)
62-
; CHECK: [[LGHI]]:addr64bit = nuw nsw LA [[LGHI]], 6, $noreg
63-
; CHECK: CGHI [[LGHI]], 0, implicit-def $cc
64-
; CHECK: BRC 14, 8, %bb.2, implicit killed $cc
65-
; CHECK: bb.7:
66-
; CHECK: successors: %bb.1(0x80000000)
67-
; CHECK: J %bb.1
31+
; CHECK-NEXT: successors: %bb.1(0x80000000)
32+
; CHECK-NEXT: {{ $}}
33+
; CHECK-NEXT: [[LGHI:%[0-9]+]]:addr64bit = LGHI -30
34+
; CHECK-NEXT: [[LHIMux:%[0-9]+]]:grx32bit = LHIMux 1
35+
; CHECK-NEXT: [[LHIMux1:%[0-9]+]]:grx32bit = LHIMux 0
36+
; CHECK-NEXT: undef [[DEF:%[0-9]+]].subreg_l32:gr64bit = IMPLICIT_DEF
37+
; CHECK-NEXT: {{ $}}
38+
; CHECK-NEXT: bb.1:
39+
; CHECK-NEXT: successors: %bb.3(0x00000001), %bb.4(0x7fffffff)
40+
; CHECK-NEXT: {{ $}}
41+
; CHECK-NEXT: CHIMux [[LHIMux]], 0, implicit-def $cc
42+
; CHECK-NEXT: BRC 14, 6, %bb.3, implicit killed $cc
43+
; CHECK-NEXT: J %bb.4
44+
; CHECK-NEXT: {{ $}}
45+
; CHECK-NEXT: bb.2:
46+
; CHECK-NEXT: successors:
47+
; CHECK-NEXT: {{ $}}
48+
; CHECK-NEXT: STMux [[DEF]].subreg_l32, undef %8:addr64bit, 0, $noreg :: (store (s32) into `ptr undef`)
49+
; CHECK-NEXT: {{ $}}
50+
; CHECK-NEXT: bb.3:
51+
; CHECK-NEXT: successors:
52+
; CHECK-NEXT: {{ $}}
53+
; CHECK-NEXT: bb.4:
54+
; CHECK-NEXT: successors: %bb.5(0x30000000), %bb.6(0x50000000)
55+
; CHECK-NEXT: {{ $}}
56+
; CHECK-NEXT: [[LAY:%[0-9]+]]:gr64bit = LAY [[LGHI]], 19838, $noreg
57+
; CHECK-NEXT: [[LAY1:%[0-9]+]]:gr64bit = LAY [[LGHI]], 19840, $noreg
58+
; CHECK-NEXT: [[LAY2:%[0-9]+]]:gr64bit = LAY [[LGHI]], 19844, $noreg
59+
; CHECK-NEXT: [[LAY2:%[0-9]+]]:gr64bit = OGR [[LAY2]], [[LAY]], implicit-def dead $cc
60+
; CHECK-NEXT: undef [[AHIMuxK:%[0-9]+]].subreg_l32:gr64bit = AHIMuxK [[LGHI]].subreg_l32, 19843, implicit-def dead $cc
61+
; CHECK-NEXT: [[AHIMuxK:%[0-9]+]]:gr64bit = ROSBG [[AHIMuxK]], [[LAY2]], 32, 63, 0, implicit-def dead $cc
62+
; CHECK-NEXT: [[DEF:%[0-9]+]].subreg_l32:gr64bit = OR [[DEF]].subreg_l32, [[AHIMuxK]].subreg_l32, implicit-def dead $cc
63+
; CHECK-NEXT: [[DEF:%[0-9]+]]:gr64bit = ROSBG [[DEF]], [[LAY1]], 32, 63, 0, implicit-def dead $cc
64+
; CHECK-NEXT: CHIMux [[LHIMux1]], 0, implicit-def $cc
65+
; CHECK-NEXT: BRC 14, 6, %bb.6, implicit killed $cc
66+
; CHECK-NEXT: J %bb.5
67+
; CHECK-NEXT: {{ $}}
68+
; CHECK-NEXT: bb.5:
69+
; CHECK-NEXT: successors: %bb.6(0x80000000)
70+
; CHECK-NEXT: {{ $}}
71+
; CHECK-NEXT: bb.6:
72+
; CHECK-NEXT: successors: %bb.2(0x00000001), %bb.7(0x7fffffff)
73+
; CHECK-NEXT: {{ $}}
74+
; CHECK-NEXT: [[LGHI:%[0-9]+]]:addr64bit = nuw nsw LA [[LGHI]], 6, $noreg
75+
; CHECK-NEXT: CGHI [[LGHI]], 0, implicit-def $cc
76+
; CHECK-NEXT: BRC 14, 8, %bb.2, implicit killed $cc
77+
; CHECK-NEXT: {{ $}}
78+
; CHECK-NEXT: bb.7:
79+
; CHECK-NEXT: successors: %bb.1(0x80000000)
80+
; CHECK-NEXT: {{ $}}
81+
; CHECK-NEXT: J %bb.1
6882
bb.0:
6983
%6:gr64bit = LGHI -30
7084
%8:grx32bit = LHIMux 1

‎llvm/test/CodeGen/SystemZ/regcoal_undefsrc.mir‎

Lines changed: 36 additions & 51 deletions
Original file line numberDiff line numberDiff line change
@@ -1,74 +1,59 @@
1-
# RUN: llc -mtriple=s390x-linux-gnu -mcpu=z13 -O3 -start-before=livevars %s -o /dev/null 2>&1
1+
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
2+
# RUN: llc -mtriple=s390x-linux-gnu -mcpu=z13 -start-before=livevars -stop-after=register-coalescer %s -o - | FileCheck %s
23
# Test that coalesing of an empty live range (undef) does not cause failure.
34

4-
--- |
5-
define dso_local void @fun(ptr %src, ptr %dst) #0 {
6-
%1 = sdiv i64 poison, poison
7-
%2 = load i32, ptr %src, align 4
8-
br i1 poison, label %6, label %3
9-
10-
3: ; preds = %0
11-
%4 = trunc i64 %1 to i32
12-
%5 = udiv i32 %4, %2
13-
br label %6
14-
15-
6: ; preds = %3, %0
16-
%7 = phi i32 [ %5, %3 ], [ 1, %0 ]
17-
store i32 %7, ptr %dst, align 4
18-
ret void
19-
}
20-
21-
...
225
---
236
name: fun
24-
alignment: 16
257
tracksRegLiveness: true
26-
registers:
27-
- { id: 0, class: gr64bit }
28-
- { id: 1, class: gr32bit }
29-
- { id: 2, class: grx32bit }
30-
- { id: 3, class: grx32bit }
31-
- { id: 4, class: addr64bit }
32-
- { id: 5, class: addr64bit }
33-
- { id: 6, class: grx32bit }
34-
- { id: 7, class: grx32bit }
35-
- { id: 8, class: grx32bit }
36-
- { id: 9, class: gr64bit }
37-
- { id: 10, class: gr64bit }
38-
- { id: 11, class: gr128bit }
39-
- { id: 12, class: gr128bit }
40-
- { id: 13, class: gr128bit }
41-
- { id: 14, class: gr128bit }
42-
- { id: 15, class: gr64bit }
43-
liveins:
44-
- { reg: '$r2d', virtual-reg: '%4' }
45-
- { reg: '$r3d', virtual-reg: '%5' }
46-
frameInfo:
47-
maxAlignment: 1
48-
machineFunctionInfo: {}
498
body: |
50-
bb.0 (%ir-block.0):
9+
; CHECK-LABEL: name: fun
10+
; CHECK: bb.0:
11+
; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)
12+
; CHECK-NEXT: liveins: $r2d, $r3d
13+
; CHECK-NEXT: {{ $}}
14+
; CHECK-NEXT: [[COPY:%[0-9]+]]:addr64bit = COPY $r3d
15+
; CHECK-NEXT: [[COPY1:%[0-9]+]]:addr64bit = COPY $r2d
16+
; CHECK-NEXT: [[LHIMux:%[0-9]+]]:grx32bit = LHIMux 1
17+
; CHECK-NEXT: [[LHIMux1:%[0-9]+]]:grx32bit = LHIMux 0
18+
; CHECK-NEXT: CHIMux [[LHIMux1]], 0, implicit-def $cc
19+
; CHECK-NEXT: BRC 14, 6, %bb.2, implicit killed $cc
20+
; CHECK-NEXT: J %bb.1
21+
; CHECK-NEXT: {{ $}}
22+
; CHECK-NEXT: bb.1:
23+
; CHECK-NEXT: successors: %bb.2(0x80000000)
24+
; CHECK-NEXT: {{ $}}
25+
; CHECK-NEXT: [[LMux:%[0-9]+]]:gr32bit = LMux [[COPY1]], 0, $noreg :: (load (s32))
26+
; CHECK-NEXT: undef [[LLILL:%[0-9]+]].subreg_h64:gr128bit = LLILL 0
27+
; CHECK-NEXT: [[LLILL:%[0-9]+]]:gr128bit = DLR [[LLILL]], [[LMux]]
28+
; CHECK-NEXT: [[LHIMux:%[0-9]+]]:grx32bit = COPY [[LLILL]].subreg_ll32
29+
; CHECK-NEXT: {{ $}}
30+
; CHECK-NEXT: bb.2:
31+
; CHECK-NEXT: STMux [[LHIMux]], [[COPY]], 0, $noreg :: (store (s32))
32+
; CHECK-NEXT: Return
33+
bb.0:
5134
liveins: $r2d, $r3d
52-
35+
5336
%5:addr64bit = COPY $r3d
5437
%4:addr64bit = COPY $r2d
5538
%6:grx32bit = LHIMux 1
5639
%7:grx32bit = LHIMux 0
5740
CHIMux killed %7, 0, implicit-def $cc
5841
BRC 14, 6, %bb.2, implicit $cc
5942
J %bb.1
60-
61-
bb.1 (%ir-block.3):
62-
%1:gr32bit = LMux %4, 0, $noreg :: (load (s32) from %ir.src)
43+
44+
bb.1:
45+
%1:gr32bit = LMux %4, 0, $noreg :: (load (s32))
6346
%15:gr64bit = LLILL 0
6447
%14:gr128bit = INSERT_SUBREG undef %13:gr128bit, %15, %subreg.subreg_h64
6548
%11:gr128bit = INSERT_SUBREG %14, undef %9:gr64bit, %subreg.subreg_l64
6649
%12:gr128bit = DLR %11, %1
6750
%2:grx32bit = COPY %12.subreg_ll32
68-
69-
bb.2 (%ir-block.6):
51+
52+
bb.2:
7053
%3:grx32bit = PHI %6, %bb.0, %2, %bb.1
71-
STMux %3, %5, 0, $noreg :: (store (s32) into %ir.dst)
54+
STMux %3, %5, 0, $noreg :: (store (s32))
7255
Return
7356
7457
...
58+
## NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
59+
# CHECK: {{.*}}

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