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kostorrpippohub
kostorr
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pippohub
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Pull bar2 registers from CRU/cru_tables.py file
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4 files changed

+224
-2
lines changed

4 files changed

+224
-2
lines changed

‎CMakeLists.txt‎

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Original file line numberDiff line numberDiff line change
@@ -55,6 +55,12 @@ ENDIF ()
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# Add compiler flags for warnings and (more importantly) fPIC and debug symbols
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set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -Wall -pedantic -Wextra -fPIC")
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58+
# Populate the Cru/Constants.h file with the register addresses contained in CRU/cru_table.py
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execute_process(COMMAND python ${CMAKE_BASE_DIR}/src/Cru/cru_constants_populate.py
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STATUS status)
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IF(NOT "${status}" EQUAL "0")
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MESSAGE(WARNING "Couldn't update CRU Register Addresses")
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ENDIF()
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####################################
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# Module, library and executable definition

‎src/Cru/Constants.h‎

Lines changed: 8 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -27,6 +27,9 @@ static constexpr size_t DMA_PAGE_SIZE = 8 * 1024;
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namespace Registers
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{
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///*** bar0 ***///
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3033
/// Control register for the data emulator
3134
/// * bit 0: Flow control
3235
static constexpr Register DMA_CONTROL(0x200);
@@ -96,6 +99,9 @@ static constexpr Register RESET_CONTROL(0x400);
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/// A debug register. The lower 8 bits of this register can be written to and read back from freely.
97100
static constexpr Register DEBUG_READ_WRITE(0x410);
98101

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///*** bar2 ***///
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99105
/// Temperature control & read register
100106
/// The lower 10 bits contain the temperature value
101107
/// Must be accessed on BAR 2
@@ -111,11 +117,11 @@ static constexpr Register FIRMWARE_EPOCH(0x1c);
111117

112118
/// Register containing the compilation date/time in seconds since Unix epoch
113119
/// Must be accessed on BAR 2
114-
static constexpr Register FIRMWARE_DATE(0x08);
120+
static constexpr Register FIRMWARE_DATE(0x00000008);
115121

116122
/// Register containing the compilation date/time in seconds since Unix epoch
117123
/// Must be accessed on BAR 2
118-
static constexpr Register FIRMWARE_TIME(0x0c);
124+
static constexpr Register FIRMWARE_TIME(0x0000000c);
119125

120126
/// Register containing the first part of the Arria 10 chip ID
121127
/// Must be accessed on BAR 2

‎src/Cru/cru_constants_populate.py‎

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Original file line numberDiff line numberDiff line change
@@ -0,0 +1,30 @@
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import fileinput
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import re
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import cru_table as table
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roc_regs = {'add_bsp_hkeeping_tempstat':'TEMPERATURE',
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'add_bsp_info_builddate':'FIRMWARE_DATE',
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'add_bsp_info_buildtime':'FIRMWARE_TIME',
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'add_bsp_hkeeping_chipid_low':'FPGA_CHIP_LOW',
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'add_bsp_hkeeping_chipid_high':'FPGA_CHIP_HIGH'}
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# e.g. 'TEMPERATURE':0x00010008
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to_replace = {}
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for key0,value0 in roc_regs.iteritems():
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for key,value in table.CRUADD.iteritems():
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if (key0 == key):
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to_replace[value0] = '0x' + str(format(value, '08x'))
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print to_replace
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cfile = open('Constants.h')
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contents = cfile.readlines()
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for key,value in to_replace.iteritems():
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for (i, line) in enumerate(contents):
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if (key in line):
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contents[i] = re.sub("\([^)]*\)", '(' + value + ')', line)
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cfile = open('Constants.h', 'w')
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cfile.writelines(contents)

‎src/Cru/cru_table.py‎

Lines changed: 180 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,180 @@
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#tag: v2.4.0
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CRUADD={'add_bsp_i2c_minipods':0x00030600,
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'add_bsp_i2c':0x00030000,
5+
'add_ttc_clkgen_lcl240freq':0x00240004,
6+
'add_bsp_hkeeping_gpi':0x00010000,
7+
'add_bsp_hkeeping':0x00010000,
8+
'add_bsp_info_shorthash':0x00000004,
9+
'add_ddg_ctrl':0x00D00000,
10+
'add_gbt_link_txclk_cnt':0x00000004,
11+
'add_patplayer_synccnt':0x00260028,
12+
'add_gbt_link_source_sel':0x00000038,
13+
'add_gbt_wrapper_clk_cnt':0x0000000C,
14+
'add_gbt_link_header_errcnt_offset':0x0000002C,
15+
'add_gbt_sca_rd_mon':0x0000001C,
16+
'add_ttc_clkgen_phasestat':0x00240024,
17+
'add_ttc_regs':0x00200000,
18+
'add_bsp_hkeeping_tempctrl':0x00010008,
19+
'add_gbt_sc':0x00F00000,
20+
'add_bsp_hkeeping_swlimit':0x0001000C,
21+
'add_bsp_info_userctrl':0x00000018,
22+
'add_gbt_link_regs_offset':0x00000000,
23+
'add_ctp_emu_hb_keep':0x0028000C,
24+
'add_bsp_info_usertxsel':0x0000001C,
25+
'add_gbt_wrapper_gregs':0x00000000,
26+
'add_bsp_hkeeping_chipid_high':0x00010014,
27+
'add_patplayer_syncpat1':0x00260014,
28+
'add_patplayer_syncpat0':0x00260010,
29+
'add_patplayer_syncpat2':0x00260018,
30+
'add_ctp_emu_hcdiv':0x00280018,
31+
'add_ttc_pon':0x00200000,
32+
'add_gbt_link_rx_err_cnt':0x0000001C,
33+
'add_dwrapper_bigfifo_lvl':0x0000000C,
34+
'add_ttc_data_ctrl':0x00200000,
35+
'add_onu_freq_meas':0x0022E000,
36+
'add_pon_wrapper_pll':0x00224000,
37+
'add_ttc_clkgen_phasecnt':0x00240020,
38+
'add_gbt_wrapper_test_control':0x00000008,
39+
'add_ttc_clkgen_ttc240freq':0x00240000,
40+
'add_gbt_link_rxframe_32lsb':0x0000000C,
41+
'add_dwrapper_drop_words':0x00000014,
42+
'add_gbt_wrapper_refclk1_freq':0x00000014,
43+
'add_dwrapper_muxctrl':0x00000004,
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'add_bsp_i2c_tsensor':0x00030000,
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'add_ctp_emu_caldiv':0x00280020,
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'add_ctp_emu_core':0x00280000,
47+
'add_dwrapper_tot_pkts':0x00000018,
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'add_userlogic_bcidmax_offset':0x00000004,
49+
'add_ttc_onu':0x00220000,
50+
'add_gbt_sca_wr_data':0x00000000,
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'add_gbt_sca_rd_cmd':0x00000014,
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'add_datalink_rej_pkt':0x0000000C,
53+
'add_mingler_linkhbid_mod':0x00000014,
54+
'add_gbt_sca_rd_ctr':0x00000018,
55+
'add_onu_user_refgen':0x0022C000,
56+
'add_datalink_offset':0x00001000,
57+
'add_ttc_clkgen_clknotokcnt':0x0024000C,
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'add_onu_refgen_cnt':0x0022C018,
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'add_patplayer_rstpat0':0x0026001C,
60+
'add_gbt_wrapper_conf1':0x00000004,
61+
'add_gbt_wrapper_conf0':0x00000000,
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'add_flowctrl_offset':0x000C0000,
63+
'add_bsp_i2c_si5344':0x00030800,
64+
'add_ttc_onu_ctrl':0x00220000,
65+
'add_bsp_info_debug':0x00000010,
66+
'add_gbt_link_mask_lo':0x00000028,
67+
'add_gbt_swt_mon':0x0000005C,
68+
'add_gbt_link_data_errcnt_offset':0x00000030,
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'add_onu_rxref_freq':0x0022E000,
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'add_gbt_sca_wr_ctr':0x00000008,
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'add_ttc_clkgen_onufpll':0x00248000,
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'add_ttc_clkgen_pllctrlonu':0x00240018,
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'add_ctp_emu_runmode':0x00280010,
74+
'add_bsp_info':0x00000000,
75+
'add_patplayer_delaycnt':0x0026002C,
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'add_bsp_i2c_sfp2':0x00030E00,
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'add_gbt_wrapper_refclk2_freq':0x00000018,
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'add_userlogic_hbbcerror_offset':0x00000008,
79+
'add_gbt_sca_wr_cmd':0x00000004,
80+
'add_ttc_clkgen_clkstat':0x00240014,
81+
'add_onu_user_logic':0x0022A000,
82+
'add_patplayer_cfg':0x00260000,
83+
'add_dwrapper_clockcore':0x00000024,
84+
'add_ddg':0x00D00000,
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'add_datalink_acc_pkt':0x00000010,
86+
'add_gbt_sca_rd_data':0x00000010,
87+
'add_datalink_ctrl':0x00000000,
88+
'add_gbt_link_xcvr_offset':0x00001000,
89+
'add_refgen1_offset':0x00000004,
90+
'add_refgen0_offset':0x00000000,
91+
'add_mingler_offset':0x00080000,
92+
'add_datapathlink_offset':0x00040000,
93+
'add_bsp_hkeeping_gpo':0x00010004,
94+
'add_onu_tx0ref_freq':0x0022E00C,
95+
'add_gbt_swt_wr_h':0x00000048,
96+
'add_dwrapper_drop_pkts':0x0000001C,
97+
'add_gbt_swt_wr_m':0x00000044,
98+
'add_gbt_swt_wr_l':0x00000040,
99+
'add_onu_rxuser_freq':0x0022E004,
100+
'add_ctp_emu_hb_max':0x00280008,
101+
'add_gbt_wrapper_refclk0_freq':0x00000010,
102+
'add_dwrapper_gregs':0x00000000,
103+
'add_ddg_pkt_cnt':0x00D00004,
104+
'add_pon_wrapper_reg':0x00222000,
105+
'add_patplayer_idlepat2':0x0026000C,
106+
'add_gbt_bank_fpll':0x0000E000,
107+
'add_patplayer_idlepat1':0x00260008,
108+
'add_ctp_emu':0x00280000,
109+
'add_dwrapper_clockcore_free':0x00000028,
110+
'add_gbt_link_rx_ctrl_offset':0x00000040,
111+
'add_datapathwrapper0':0x00600000,
112+
'add_datapathwrapper1':0x00700000,
113+
'add_bsp':0x00000000,
114+
'add_userlogic_errcntall_offset':0x0000000C,
115+
'add_gbt_wrapper1':0x00500000,
116+
'add_gbt_wrapper0':0x00400000,
117+
'add_ttc_clkgen_clkctrl':0x00240010,
118+
'add_userlogic_ctrl_offset':0x00000000,
119+
'add_ttc_clkgen_ref240freq':0x00240008,
120+
'add_bsp_i2c_si5345_1':0x00030A00,
121+
'add_bsp_i2c_si5345_2':0x00030C00,
122+
'add_patplayer_debug':0x00260038,
123+
'add_mingler_linkid_mod':0x0000000C,
124+
'add_onu_tx2ref_freq':0x0022E014,
125+
'add_patplayer_idlepat0':0x00260004,
126+
'add_gbt_link_fec_monitoring':0x0000003C,
127+
'add_gbt_wrapper_refclk3_freq':0x0000001C,
128+
'add_patplayer_trigsel':0x00260034,
129+
'add_flowctrl_pkt_tot':0x00000008,
130+
'add_bsp_info_builddate':0x00000008,
131+
'add_onu_tx1ref_freq':0x0022E010,
132+
'add_mingler_linkhbid':0x00000008,
133+
'add_flowctrl_ctrlreg':0x00000000,
134+
'add_ctp_emu_userbits':0x0028001C,
135+
'add_dwrapper_enreg':0x00000000,
136+
'add_pon_wrapper_tx':0x00226000,
137+
'add_bsp_info_dirtystatus':0x00000000,
138+
'add_gbt_wrapper_bank_offset':0x00020000,
139+
'add_patplayer_rstcnt':0x00260030,
140+
'add_gbt_link_tx_ctrl_offset':0x00000034,
141+
'add_bsp_hkeeping_hwlimit':0x00010010,
142+
'add_ttc_clkgen_pllstatonu':0x0024001C,
143+
'add_gbt_link_dbgdata0':0x00000010,
144+
'add_gbt_link_dbgdata2':0x00000018,
145+
'add_gbt_swt_cmd':0x0000004C,
146+
'add_bsp_info_buildtime':0x0000000C,
147+
'add_datalink_forced_pkt':0x00000014,
148+
'add_gbt_link_status':0x00000000,
149+
'add_onu_tx3ref_freq':0x0022E018,
150+
'add_gbt_link_mask_med':0x00000024,
151+
'add_ctp_emu_physdiv':0x00280014,
152+
'add_ttc_patplayer':0x00260000,
153+
'add_bsp_i2c_cpcie':0x00030200,
154+
'add_pon_verinfo':0x00220000,
155+
'add_patplayer_rstpat2':0x00260024,
156+
'add_gbt_sc_rst':0x00000064,
157+
'add_patplayer_rstpat1':0x00260020,
158+
'add_gbt_bank_link_offset':0x00002000,
159+
'add_gbt_sc_link':0x00000060,
160+
'add_bsp_hkeeping_tempstat':0x00010008,
161+
'add_ctp_emu_ctrl':0x00280000,
162+
'add_mingler_linkid':0x00000000,
163+
'add_bsp_i2c_sfp1':0x00030400,
164+
'add_gbt_link_mask_hi':0x00000020,
165+
'add_ttc_clkgen':0x00240000,
166+
'add_userlogic':0x00C00000,
167+
'add_gbt_swt_rd_h':0x00000058,
168+
'add_flowctrl_pkt_rej':0x00000004,
169+
'add_gbt_swt_rd_l':0x00000050,
170+
'add_gbt_swt_rd_m':0x00000054,
171+
'add_ctp_emu_bc_max':0x00280004,
172+
'add_gbt_link_dbgdata1':0x00000014,
173+
'add_bsp_hkeeping_chipid_low':0x00010018,
174+
'add_onu_txuser_freq':0x0022E01C,
175+
'add_gbt_link_rxclk_cnt':0x00000008,
176+
'add_dwrapper_tot_words':0x00000010,
177+
'add_dwrapper_lasthbid':0x00000020,
178+
'add_gbt_wrapper_atx_pll':0x000E0000,
179+
'add_onu_refout_freq':0x0022E008,
180+
}

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