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Merge tag 'reset-for-v5.15' of git://git.pengutronix.de/pza/linux into arm/drivers
Reset controller updates for v5.15 Add support for the SC7280 PDC Global and RZ/G2L USB/PHY reset controllers, convert UniPhier glue device tree bindings to json-schema and remove a leftover mention of ZTE zx2967 from Kconfig. * tag 'reset-for-v5.15' of git://git.pengutronix.de/pza/linux: reset: simple: remove ZTE details in Kconfig help reset: renesas: Add RZ/G2L usbphy control driver dt-bindings: reset: Document RZ/G2L USBPHY Control bindings dt-bindings: reset: Convert UniPhier glue reset to json-schema reset: qcom: Add PDC Global reset signals for WPSS dt-bindings: reset: pdc: Add PDC Global bindings dt-bindings: reset: aoss: Add AOSS reset controller binding Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Arnd Bergmann <[email protected]>
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‎Documentation/devicetree/bindings/reset/qcom,aoss-reset.yaml

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- const: "qcom,sc7180-aoss-cc"
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- const: "qcom,sdm845-aoss-cc"
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- description: on SC7280 SoCs the following compatibles must be specified
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items:
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- const: "qcom,sc7280-aoss-cc"
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- const: "qcom,sdm845-aoss-cc"
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- description: on SDM845 SoCs the following compatibles must be specified
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items:
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- const: "qcom,sdm845-aoss-cc"

‎Documentation/devicetree/bindings/reset/qcom,pdc-global.yaml

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- const: "qcom,sc7180-pdc-global"
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- const: "qcom,sdm845-pdc-global"
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- description: on SC7280 SoCs the following compatibles must be specified
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items:
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- const: "qcom,sc7280-pdc-global"
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- description: on SDM845 SoCs the following compatibles must be specified
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items:
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- const: "qcom,sdm845-pdc-global"

‎Documentation/devicetree/bindings/reset/renesas,rzg2l-usbphy-ctrl.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/reset/renesas,rzg2l-usbphy-ctrl.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Renesas RZ/G2L USBPHY Control
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maintainers:
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- Biju Das <[email protected]>
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description:
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The RZ/G2L USBPHY Control mainly controls reset and power down of the
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USB/PHY.
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properties:
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compatible:
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items:
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- enum:
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- renesas,r9a07g044-usbphy-ctrl # RZ/G2{L,LC}
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- const: renesas,rzg2l-usbphy-ctrl
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reg:
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maxItems: 1
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clocks:
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maxItems: 1
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resets:
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maxItems: 1
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power-domains:
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maxItems: 1
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'#reset-cells':
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const: 1
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description: |
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The phandle's argument in the reset specifier is the PHY reset associated
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with the USB port.
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0 = Port 1 Phy reset
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1 = Port 2 Phy reset
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required:
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- compatible
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- reg
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- clocks
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- resets
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- power-domains
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- '#reset-cells'
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/r9a07g044-cpg.h>
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phyrst: usbphy-ctrl@11c40000 {
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compatible = "renesas,r9a07g044-usbphy-ctrl",
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"renesas,rzg2l-usbphy-ctrl";
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reg = <0x11c40000 0x10000>;
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clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>;
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resets = <&cpg R9A07G044_USB_PRESETN>;
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power-domains = <&cpg>;
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#reset-cells = <1>;
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};

‎Documentation/devicetree/bindings/reset/socionext,uniphier-glue-reset.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/reset/socionext,uniphier-glue-reset.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Socionext UniPhier peripheral core reset in glue layer
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description: |
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Some peripheral core reset belongs to its own glue layer. Before using
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this core reset, it is necessary to control the clocks and resets to
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enable this layer. These clocks and resets should be described in each
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property.
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maintainers:
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- Kunihiko Hayashi <[email protected]>
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properties:
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compatible:
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enum:
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- socionext,uniphier-pro4-usb3-reset
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- socionext,uniphier-pro5-usb3-reset
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- socionext,uniphier-pxs2-usb3-reset
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- socionext,uniphier-ld20-usb3-reset
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- socionext,uniphier-pxs3-usb3-reset
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- socionext,uniphier-pro4-ahci-reset
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- socionext,uniphier-pxs2-ahci-reset
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- socionext,uniphier-pxs3-ahci-reset
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reg:
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maxItems: 1
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"#reset-cells":
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const: 1
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clocks:
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minItems: 1
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maxItems: 2
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clock-names:
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oneOf:
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- items: # for Pro4, Pro5
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- const: gio
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- const: link
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- items: # for others
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- const: link
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resets:
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minItems: 1
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maxItems: 2
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reset-names:
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oneOf:
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- items: # for Pro4, Pro5
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- const: gio
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- const: link
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- items: # for others
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- const: link
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additionalProperties: false
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required:
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- compatible
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- reg
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- "#reset-cells"
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- clocks
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- clock-names
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- resets
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- reset-names
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examples:
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- |
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usb-glue@65b00000 {
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compatible = "simple-mfd";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x65b00000 0x400>;
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usb_rst: reset@0 {
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compatible = "socionext,uniphier-ld20-usb3-reset";
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reg = <0x0 0x4>;
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#reset-cells = <1>;
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clock-names = "link";
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clocks = <&sys_clk 14>;
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reset-names = "link";
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resets = <&sys_rst 14>;
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};
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};

‎Documentation/devicetree/bindings/reset/uniphier-reset.txt

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‎drivers/reset/Kconfig

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interfacing with RPi4's co-processor and model these firmware
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initialization routines as reset lines.
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config RESET_RZG2L_USBPHY_CTRL
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tristate "Renesas RZ/G2L USBPHY control driver"
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depends on ARCH_R9A07G044 || COMPILE_TEST
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help
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Support for USBPHY Control found on RZ/G2L family. It mainly
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controls reset and power down of the USB/PHY.
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config RESET_SCMI
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tristate "Reset driver controlled via ARM SCMI interface"
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depends on ARM_SCMI_PROTOCOL || COMPILE_TEST
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- Realtek SoCs
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- RCC reset controller in STM32 MCUs
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- Allwinner SoCs
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- ZTE's zx2967 family
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- SiFive FU740 SoCs
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config RESET_SOCFPGA

‎drivers/reset/Makefile

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obj-$(CONFIG_RESET_QCOM_AOSS) += reset-qcom-aoss.o
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obj-$(CONFIG_RESET_QCOM_PDC) += reset-qcom-pdc.o
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obj-$(CONFIG_RESET_RASPBERRYPI) += reset-raspberrypi.o
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obj-$(CONFIG_RESET_RZG2L_USBPHY_CTRL) += reset-rzg2l-usbphy-ctrl.o
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obj-$(CONFIG_RESET_SCMI) += reset-scmi.o
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obj-$(CONFIG_RESET_SIMPLE) += reset-simple.o
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obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o

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