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Michael Straussalexdeucher
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drm/amd/display: Add link rate optimization logs for ILR
[Why&How] Add logs to verify ILR optimization behaviour on boot Signed-off-by: Michael Strauss <[email protected]> Reviewed-by: Nicholas Kazlauskas <[email protected]> Acked-by: Aurabindo Pillai <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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-2
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3 files changed

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drivers/gpu/drm/amd/display/dc/core/dc.c

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1434,6 +1434,7 @@ bool dc_validate_seamless_boot_timing(const struct dc *dc,
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}
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if (is_edp_ilr_optimization_required(link, crtc_timing)) {
1437+
DC_LOG_EVENT_LINK_TRAINING("Seamless boot disabled to optimize eDP link rate\n");
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return false;
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}
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drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c

Lines changed: 7 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -4739,8 +4739,10 @@ bool is_edp_ilr_optimization_required(struct dc_link *link, struct dc_crtc_timin
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core_link_read_dpcd(link, DP_LINK_BW_SET,
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&link_bw_set, sizeof(link_bw_set));
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4742-
if (link_bw_set)
4742+
if (link_bw_set) {
4743+
DC_LOG_EVENT_LINK_TRAINING("eDP ILR: Optimization required, VBIOS used link_bw_set\n");
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return true;
4745+
}
47444746

47454747
// Read DPCD 00115h to find the edp link rate set used
47464748
core_link_read_dpcd(link, DP_LINK_RATE_SET,
@@ -4755,9 +4757,12 @@ bool is_edp_ilr_optimization_required(struct dc_link *link, struct dc_crtc_timin
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decide_edp_link_settings(link, &link_setting, req_bw);
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47574759
if (link->dpcd_caps.edp_supported_link_rates[link_rate_set] != link_setting.link_rate ||
4758-
lane_count_set.bits.LANE_COUNT_SET != link_setting.lane_count)
4760+
lane_count_set.bits.LANE_COUNT_SET != link_setting.lane_count) {
4761+
DC_LOG_EVENT_LINK_TRAINING("eDP ILR: Optimization required, VBIOS link_rate_set not optimal\n");
47594762
return true;
4763+
}
47604764

4765+
DC_LOG_EVENT_LINK_TRAINING("eDP ILR: No optimization required, VBIOS set optimal link_rate_set\n");
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return false;
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}
47634768

drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1695,6 +1695,8 @@ void dce110_enable_accelerated_mode(struct dc *dc, struct dc_state *context)
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bool can_apply_edp_fast_boot = false;
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bool can_apply_seamless_boot = false;
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bool keep_edp_vdd_on = false;
1698+
DC_LOGGER_INIT();
1699+
16981700

16991701
get_edp_links_with_sink(dc, edp_links_with_sink, &edp_with_sink_num);
17001702
get_edp_links(dc, edp_links, &edp_num);
@@ -1717,6 +1719,8 @@ void dce110_enable_accelerated_mode(struct dc *dc, struct dc_state *context)
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edp_stream = edp_streams[0];
17181720
can_apply_edp_fast_boot = !is_edp_ilr_optimization_required(edp_stream->link, &edp_stream->timing);
17191721
edp_stream->apply_edp_fast_boot_optimization = can_apply_edp_fast_boot;
1722+
if (can_apply_edp_fast_boot)
1723+
DC_LOG_EVENT_LINK_TRAINING("eDP fast boot disabled to optimize link rate\n");
17201724

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break;
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}

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