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dt-bindings: clk: qcom: gcc-sm6125: Document SM6125 GCC driver
Document the newly added SM6125 GCC driver. Signed-off-by: Martin Botka <[email protected]> Link: https://lore.kernel.org/r/[email protected] Reviewed-by: Rob Herring <[email protected]> Reviewed-by: Bjorn Andersson <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
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‎Documentation/devicetree/bindings/clock/qcom,gcc-sm6125.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/qcom,gcc-sm6125.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Global Clock & Reset Controller Binding for SM6125
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maintainers:
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- Konrad Dybcio <[email protected]>
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description: |
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Qualcomm global clock control module which supports the clocks, resets and
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power domains on SM6125.
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See also:
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- dt-bindings/clock/qcom,gcc-sm6125.h
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properties:
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compatible:
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const: qcom,gcc-sm6125
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clocks:
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items:
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- description: Board XO source
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- description: Sleep clock source
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clock-names:
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items:
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- const: bi_tcxo
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- const: sleep_clk
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'#clock-cells':
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const: 1
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'#reset-cells':
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const: 1
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'#power-domain-cells':
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const: 1
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reg:
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maxItems: 1
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protected-clocks:
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description:
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Protected clock specifier list as per common clock binding.
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required:
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- compatible
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- clocks
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- clock-names
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- reg
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- '#clock-cells'
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- '#reset-cells'
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- '#power-domain-cells'
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,rpmcc.h>
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clock-controller@1400000 {
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compatible = "qcom,gcc-sm6125";
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reg = <0x01400000 0x1f0000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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#power-domain-cells = <1>;
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clock-names = "bi_tcxo", "sleep_clk";
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clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&sleep_clk>;
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};
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...

‎include/dt-bindings/clock/qcom,gcc-sm6125.h

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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/*
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* Copyright (c) 2021, Konrad Dybcio <[email protected]>
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*/
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#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SM6125_H
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#define _DT_BINDINGS_CLK_QCOM_GCC_SM6125_H
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#define GPLL0_OUT_AUX2 0
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#define GPLL0_OUT_MAIN 1
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#define GPLL6_OUT_MAIN 2
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#define GPLL7_OUT_MAIN 3
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#define GPLL8_OUT_MAIN 4
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#define GPLL9_OUT_MAIN 5
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#define GPLL0_OUT_EARLY 6
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#define GPLL3_OUT_EARLY 7
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#define GPLL4_OUT_MAIN 8
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#define GPLL5_OUT_MAIN 9
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#define GPLL6_OUT_EARLY 10
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#define GPLL7_OUT_EARLY 11
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#define GPLL8_OUT_EARLY 12
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#define GPLL9_OUT_EARLY 13
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#define GCC_AHB2PHY_CSI_CLK 14
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#define GCC_AHB2PHY_USB_CLK 15
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#define GCC_APC_VS_CLK 16
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#define GCC_BOOT_ROM_AHB_CLK 17
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#define GCC_CAMERA_AHB_CLK 18
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#define GCC_CAMERA_XO_CLK 19
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#define GCC_CAMSS_AHB_CLK_SRC 20
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#define GCC_CAMSS_CCI_AHB_CLK 21
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#define GCC_CAMSS_CCI_CLK 22
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#define GCC_CAMSS_CCI_CLK_SRC 23
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#define GCC_CAMSS_CPHY_CSID0_CLK 24
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#define GCC_CAMSS_CPHY_CSID1_CLK 25
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#define GCC_CAMSS_CPHY_CSID2_CLK 26
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#define GCC_CAMSS_CPHY_CSID3_CLK 27
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#define GCC_CAMSS_CPP_AHB_CLK 28
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#define GCC_CAMSS_CPP_AXI_CLK 29
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#define GCC_CAMSS_CPP_CLK 30
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#define GCC_CAMSS_CPP_CLK_SRC 31
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#define GCC_CAMSS_CPP_VBIF_AHB_CLK 32
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#define GCC_CAMSS_CSI0_AHB_CLK 33
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#define GCC_CAMSS_CSI0_CLK 34
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#define GCC_CAMSS_CSI0_CLK_SRC 35
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#define GCC_CAMSS_CSI0PHYTIMER_CLK 36
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#define GCC_CAMSS_CSI0PHYTIMER_CLK_SRC 37
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#define GCC_CAMSS_CSI0PIX_CLK 38
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#define GCC_CAMSS_CSI0RDI_CLK 39
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#define GCC_CAMSS_CSI1_AHB_CLK 40
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#define GCC_CAMSS_CSI1_CLK 41
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#define GCC_CAMSS_CSI1_CLK_SRC 42
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#define GCC_CAMSS_CSI1PHYTIMER_CLK 43
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#define GCC_CAMSS_CSI1PHYTIMER_CLK_SRC 44
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#define GCC_CAMSS_CSI1PIX_CLK 45
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#define GCC_CAMSS_CSI1RDI_CLK 46
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#define GCC_CAMSS_CSI2_AHB_CLK 47
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#define GCC_CAMSS_CSI2_CLK 48
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#define GCC_CAMSS_CSI2_CLK_SRC 49
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#define GCC_CAMSS_CSI2PHYTIMER_CLK 50
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#define GCC_CAMSS_CSI2PHYTIMER_CLK_SRC 51
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#define GCC_CAMSS_CSI2PIX_CLK 52
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#define GCC_CAMSS_CSI2RDI_CLK 53
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#define GCC_CAMSS_CSI3_AHB_CLK 54
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#define GCC_CAMSS_CSI3_CLK 55
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#define GCC_CAMSS_CSI3_CLK_SRC 56
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#define GCC_CAMSS_CSI3PIX_CLK 57
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#define GCC_CAMSS_CSI3RDI_CLK 58
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#define GCC_CAMSS_CSI_VFE0_CLK 59
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#define GCC_CAMSS_CSI_VFE1_CLK 60
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#define GCC_CAMSS_CSIPHY0_CLK 61
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#define GCC_CAMSS_CSIPHY1_CLK 62
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#define GCC_CAMSS_CSIPHY2_CLK 63
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#define GCC_CAMSS_CSIPHY_CLK_SRC 64
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#define GCC_CAMSS_GP0_CLK 65
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#define GCC_CAMSS_GP0_CLK_SRC 66
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#define GCC_CAMSS_GP1_CLK 67
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#define GCC_CAMSS_GP1_CLK_SRC 68
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#define GCC_CAMSS_ISPIF_AHB_CLK 69
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#define GCC_CAMSS_JPEG_AHB_CLK 70
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#define GCC_CAMSS_JPEG_AXI_CLK 71
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#define GCC_CAMSS_JPEG_CLK 72
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#define GCC_CAMSS_JPEG_CLK_SRC 73
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#define GCC_CAMSS_MCLK0_CLK 74
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#define GCC_CAMSS_MCLK0_CLK_SRC 75
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#define GCC_CAMSS_MCLK1_CLK 76
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#define GCC_CAMSS_MCLK1_CLK_SRC 77
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#define GCC_CAMSS_MCLK2_CLK 78
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#define GCC_CAMSS_MCLK2_CLK_SRC 79
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#define GCC_CAMSS_MCLK3_CLK 80
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#define GCC_CAMSS_MCLK3_CLK_SRC 81
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#define GCC_CAMSS_MICRO_AHB_CLK 82
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#define GCC_CAMSS_THROTTLE_NRT_AXI_CLK 83
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#define GCC_CAMSS_THROTTLE_RT_AXI_CLK 84
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#define GCC_CAMSS_TOP_AHB_CLK 85
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#define GCC_CAMSS_VFE0_AHB_CLK 86
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#define GCC_CAMSS_VFE0_CLK 87
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#define GCC_CAMSS_VFE0_CLK_SRC 88
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#define GCC_CAMSS_VFE0_STREAM_CLK 89
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#define GCC_CAMSS_VFE1_AHB_CLK 90
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#define GCC_CAMSS_VFE1_CLK 91
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#define GCC_CAMSS_VFE1_CLK_SRC 92
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#define GCC_CAMSS_VFE1_STREAM_CLK 93
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#define GCC_CAMSS_VFE_TSCTR_CLK 94
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#define GCC_CAMSS_VFE_VBIF_AHB_CLK 95
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#define GCC_CAMSS_VFE_VBIF_AXI_CLK 96
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#define GCC_CE1_AHB_CLK 97
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#define GCC_CE1_AXI_CLK 98
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#define GCC_CE1_CLK 99
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#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 100
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#define GCC_CPUSS_GNOC_CLK 101
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#define GCC_DISP_AHB_CLK 102
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#define GCC_DISP_GPLL0_DIV_CLK_SRC 103
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#define GCC_DISP_HF_AXI_CLK 104
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#define GCC_DISP_THROTTLE_CORE_CLK 105
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#define GCC_DISP_XO_CLK 106
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#define GCC_GP1_CLK 107
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#define GCC_GP1_CLK_SRC 108
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#define GCC_GP2_CLK 109
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#define GCC_GP2_CLK_SRC 110
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#define GCC_GP3_CLK 111
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#define GCC_GP3_CLK_SRC 112
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#define GCC_GPU_CFG_AHB_CLK 113
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#define GCC_GPU_GPLL0_CLK_SRC 114
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#define GCC_GPU_GPLL0_DIV_CLK_SRC 115
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#define GCC_GPU_MEMNOC_GFX_CLK 116
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#define GCC_GPU_SNOC_DVM_GFX_CLK 117
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#define GCC_GPU_THROTTLE_CORE_CLK 118
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#define GCC_GPU_THROTTLE_XO_CLK 119
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#define GCC_MSS_VS_CLK 120
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#define GCC_PDM2_CLK 121
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#define GCC_PDM2_CLK_SRC 122
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#define GCC_PDM_AHB_CLK 123
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#define GCC_PDM_XO4_CLK 124
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#define GCC_PRNG_AHB_CLK 125
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#define GCC_QMIP_CAMERA_NRT_AHB_CLK 126
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#define GCC_QMIP_CAMERA_RT_AHB_CLK 127
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#define GCC_QMIP_DISP_AHB_CLK 128
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#define GCC_QMIP_GPU_CFG_AHB_CLK 129
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#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 130
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#define GCC_QUPV3_WRAP0_CORE_2X_CLK 131
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#define GCC_QUPV3_WRAP0_CORE_CLK 132
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#define GCC_QUPV3_WRAP0_S0_CLK 133
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#define GCC_QUPV3_WRAP0_S0_CLK_SRC 134
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#define GCC_QUPV3_WRAP0_S1_CLK 135
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#define GCC_QUPV3_WRAP0_S1_CLK_SRC 136
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#define GCC_QUPV3_WRAP0_S2_CLK 137
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#define GCC_QUPV3_WRAP0_S2_CLK_SRC 138
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#define GCC_QUPV3_WRAP0_S3_CLK 139
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#define GCC_QUPV3_WRAP0_S3_CLK_SRC 140
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#define GCC_QUPV3_WRAP0_S4_CLK 141
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#define GCC_QUPV3_WRAP0_S4_CLK_SRC 142
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#define GCC_QUPV3_WRAP0_S5_CLK 143
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#define GCC_QUPV3_WRAP0_S5_CLK_SRC 144
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#define GCC_QUPV3_WRAP1_CORE_2X_CLK 145
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#define GCC_QUPV3_WRAP1_CORE_CLK 146
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#define GCC_QUPV3_WRAP1_S0_CLK 147
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#define GCC_QUPV3_WRAP1_S0_CLK_SRC 148
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#define GCC_QUPV3_WRAP1_S1_CLK 149
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#define GCC_QUPV3_WRAP1_S1_CLK_SRC 150
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#define GCC_QUPV3_WRAP1_S2_CLK 151
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#define GCC_QUPV3_WRAP1_S2_CLK_SRC 152
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#define GCC_QUPV3_WRAP1_S3_CLK 153
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#define GCC_QUPV3_WRAP1_S3_CLK_SRC 154
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#define GCC_QUPV3_WRAP1_S4_CLK 155
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#define GCC_QUPV3_WRAP1_S4_CLK_SRC 156
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#define GCC_QUPV3_WRAP1_S5_CLK 157
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#define GCC_QUPV3_WRAP1_S5_CLK_SRC 158
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#define GCC_QUPV3_WRAP_0_M_AHB_CLK 159
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#define GCC_QUPV3_WRAP_0_S_AHB_CLK 160
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#define GCC_QUPV3_WRAP_1_M_AHB_CLK 161
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#define GCC_QUPV3_WRAP_1_S_AHB_CLK 162
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#define GCC_SDCC1_AHB_CLK 163
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#define GCC_SDCC1_APPS_CLK 164
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#define GCC_SDCC1_APPS_CLK_SRC 165
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#define GCC_SDCC1_ICE_CORE_CLK 166
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#define GCC_SDCC1_ICE_CORE_CLK_SRC 167
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#define GCC_SDCC2_AHB_CLK 168
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#define GCC_SDCC2_APPS_CLK 169
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#define GCC_SDCC2_APPS_CLK_SRC 170
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#define GCC_SYS_NOC_CPUSS_AHB_CLK 171
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#define GCC_SYS_NOC_UFS_PHY_AXI_CLK 172
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#define GCC_SYS_NOC_USB3_PRIM_AXI_CLK 173
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#define GCC_UFS_PHY_AHB_CLK 174
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#define GCC_UFS_PHY_AXI_CLK 175
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#define GCC_UFS_PHY_AXI_CLK_SRC 176
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#define GCC_UFS_PHY_ICE_CORE_CLK 177
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#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 178
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#define GCC_UFS_PHY_PHY_AUX_CLK 179
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#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 180
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#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 181
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#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 182
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#define GCC_UFS_PHY_UNIPRO_CORE_CLK 183
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#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 184
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#define GCC_USB30_PRIM_MASTER_CLK 185
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#define GCC_USB30_PRIM_MASTER_CLK_SRC 186
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#define GCC_USB30_PRIM_MOCK_UTMI_CLK 187
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#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 188
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#define GCC_USB30_PRIM_SLEEP_CLK 189
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#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 190
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#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 191
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#define GCC_USB3_PRIM_PHY_PIPE_CLK 192
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#define GCC_VDDA_VS_CLK 193
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#define GCC_VDDCX_VS_CLK 194
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#define GCC_VDDMX_VS_CLK 195
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#define GCC_VIDEO_AHB_CLK 196
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#define GCC_VIDEO_AXI0_CLK 197
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#define GCC_VIDEO_THROTTLE_CORE_CLK 198
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#define GCC_VIDEO_XO_CLK 199
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#define GCC_VS_CTRL_AHB_CLK 200
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#define GCC_VS_CTRL_CLK 201
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#define GCC_VS_CTRL_CLK_SRC 202
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#define GCC_VSENSOR_CLK_SRC 203
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#define GCC_WCSS_VS_CLK 204
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#define GCC_USB3_PRIM_CLKREF_CLK 205
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#define GCC_SYS_NOC_COMPUTE_SF_AXI_CLK 206
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#define GCC_BIMC_GPU_AXI_CLK 207
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#define GCC_UFS_MEM_CLKREF_CLK 208
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/* GDSCs */
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#define USB30_PRIM_GDSC 0
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#define UFS_PHY_GDSC 1
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#define CAMSS_VFE0_GDSC 2
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#define CAMSS_VFE1_GDSC 3
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#define CAMSS_TOP_GDSC 4
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#define CAM_CPP_GDSC 5
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#define HLOS1_VOTE_TURING_MMU_TBU1_GDSC 6
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#define HLOS1_VOTE_MM_SNOC_MMU_TBU_RT_GDSC 7
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#define HLOS1_VOTE_MM_SNOC_MMU_TBU_NRT_GDSC 8
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#define HLOS1_VOTE_TURING_MMU_TBU0_GDSC 9
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#define GCC_QUSB2PHY_PRIM_BCR 0
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#define GCC_QUSB2PHY_SEC_BCR 1
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#define GCC_UFS_PHY_BCR 2
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#define GCC_USB30_PRIM_BCR 3
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#define GCC_USB_PHY_CFG_AHB2PHY_BCR 4
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#define GCC_USB3_PHY_PRIM_SP0_BCR 5
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#define GCC_USB3PHY_PHY_PRIM_SP0_BCR 6
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#define GCC_CAMSS_MICRO_BCR 7
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#endif

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