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ichernevvinodkoul
ichernev
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phy: qcom-qmp: Add support for SM6115 UFS phy
Add the tables and constants for init sequences for UFS QMP phy found in SM4250/6115 SoC. The phy is a variation of the v2 phy, but is mistakenly labeled as v3-660 in downstream sources. QSERDES COM, RX, TX registers match fully existing v2 registers, with a few additions. PCS registers don't have much in common, but there are no clashes with existing ones so new registers were added to existing v2 PCS pack. Signed-off-by: Iskren Chernev <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
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‎drivers/phy/qualcomm/phy-qcom-qmp.c

Lines changed: 124 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -234,6 +234,11 @@ static const unsigned int sdm845_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
234234
[QPHY_PCS_READY_STATUS] = 0x160,
235235
};
236236

237+
static const unsigned int sm6115_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
238+
[QPHY_START_CTRL] = 0x00,
239+
[QPHY_PCS_READY_STATUS] = 0x168,
240+
};
241+
237242
static const unsigned int sm8250_pcie_regs_layout[QPHY_LAYOUT_SIZE] = {
238243
[QPHY_SW_RESET] = 0x00,
239244
[QPHY_START_CTRL] = 0x44,
@@ -1329,6 +1334,97 @@ static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_pcs_tbl[] = {
13291334
QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG2, 0x60),
13301335
};
13311336

1337+
static const struct qmp_phy_init_tbl sm6115_ufsphy_serdes_tbl[] = {
1338+
QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e),
1339+
QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
1340+
QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
1341+
QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x02),
1342+
QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
1343+
QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
1344+
QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
1345+
QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
1346+
QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a),
1347+
QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x01),
1348+
QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00),
1349+
QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
1350+
QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
1351+
QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
1352+
QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
1353+
QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f),
1354+
QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x04),
1355+
QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05),
1356+
QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
1357+
QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00),
1358+
QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00),
1359+
QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00),
1360+
QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
1361+
QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
1362+
QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
1363+
QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
1364+
QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
1365+
QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE0, 0x28),
1366+
QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE0, 0x02),
1367+
QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xff),
1368+
QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c),
1369+
QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
1370+
QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE1, 0x98),
1371+
QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00),
1372+
QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00),
1373+
QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00),
1374+
QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE1, 0x0b),
1375+
QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE1, 0x16),
1376+
QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE1, 0x28),
1377+
QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80),
1378+
QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
1379+
QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE1, 0xd6),
1380+
QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE1, 0x00),
1381+
QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE1, 0x32),
1382+
QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f),
1383+
QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00),
1384+
QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
1385+
QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
1386+
QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL1, 0xff),
1387+
QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL2, 0x00),
1388+
1389+
/* Rate B */
1390+
QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x44),
1391+
};
1392+
1393+
static const struct qmp_phy_init_tbl sm6115_ufsphy_tx_tbl[] = {
1394+
QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
1395+
QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
1396+
};
1397+
1398+
static const struct qmp_phy_init_tbl sm6115_ufsphy_rx_tbl[] = {
1399+
QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24),
1400+
QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x0F),
1401+
QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x40),
1402+
QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x1E),
1403+
QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B),
1404+
QMP_PHY_INIT_CFG(QSERDES_RX_RX_TERM_BW, 0x5B),
1405+
QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xFF),
1406+
QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3F),
1407+
QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xFF),
1408+
QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x3F),
1409+
QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0D),
1410+
QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN_HALF, 0x04),
1411+
QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04),
1412+
QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN, 0x04),
1413+
QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5B),
1414+
};
1415+
1416+
static const struct qmp_phy_init_tbl sm6115_ufsphy_pcs_tbl[] = {
1417+
QMP_PHY_INIT_CFG(QPHY_RX_PWM_GEAR_BAND, 0x15),
1418+
QMP_PHY_INIT_CFG(QPHY_RX_SIGDET_CTRL2, 0x6d),
1419+
QMP_PHY_INIT_CFG(QPHY_TX_LARGE_AMP_DRV_LVL, 0x0f),
1420+
QMP_PHY_INIT_CFG(QPHY_TX_SMALL_AMP_DRV_LVL, 0x02),
1421+
QMP_PHY_INIT_CFG(QPHY_RX_MIN_STALL_NOCONFIG_TIME_CAP, 0x28),
1422+
QMP_PHY_INIT_CFG(QPHY_RX_SYM_RESYNC_CTRL, 0x03),
1423+
QMP_PHY_INIT_CFG(QPHY_TX_LARGE_AMP_POST_EMP_LVL, 0x12),
1424+
QMP_PHY_INIT_CFG(QPHY_TX_SMALL_AMP_POST_EMP_LVL, 0x0f),
1425+
QMP_PHY_INIT_CFG(QPHY_RX_MIN_HIBERN8_TIME, 0x9a), /* 8 us */
1426+
};
1427+
13321428
static const struct qmp_phy_init_tbl sdm845_ufsphy_serdes_tbl[] = {
13331429
QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
13341430
QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
@@ -3396,6 +3492,31 @@ static const struct qmp_phy_cfg sdm845_ufsphy_cfg = {
33963492
.no_pcs_sw_reset = true,
33973493
};
33983494

3495+
static const struct qmp_phy_cfg sm6115_ufsphy_cfg = {
3496+
.type = PHY_TYPE_UFS,
3497+
.nlanes = 1,
3498+
3499+
.serdes_tbl = sm6115_ufsphy_serdes_tbl,
3500+
.serdes_tbl_num = ARRAY_SIZE(sm6115_ufsphy_serdes_tbl),
3501+
.tx_tbl = sm6115_ufsphy_tx_tbl,
3502+
.tx_tbl_num = ARRAY_SIZE(sm6115_ufsphy_tx_tbl),
3503+
.rx_tbl = sm6115_ufsphy_rx_tbl,
3504+
.rx_tbl_num = ARRAY_SIZE(sm6115_ufsphy_rx_tbl),
3505+
.pcs_tbl = sm6115_ufsphy_pcs_tbl,
3506+
.pcs_tbl_num = ARRAY_SIZE(sm6115_ufsphy_pcs_tbl),
3507+
.clk_list = sdm845_ufs_phy_clk_l,
3508+
.num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
3509+
.vreg_list = qmp_phy_vreg_l,
3510+
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
3511+
.regs = sm6115_ufsphy_regs_layout,
3512+
3513+
.start_ctrl = SERDES_START,
3514+
.pwrdn_ctrl = SW_PWRDN,
3515+
3516+
.is_dual_lane_phy = false,
3517+
.no_pcs_sw_reset = true,
3518+
};
3519+
33993520
static const struct qmp_phy_cfg msm8998_pciephy_cfg = {
34003521
.type = PHY_TYPE_PCIE,
34013522
.nlanes = 1,
@@ -5444,6 +5565,9 @@ static const struct of_device_id qcom_qmp_phy_of_match_table[] = {
54445565
}, {
54455566
.compatible = "qcom,msm8998-qmp-usb3-phy",
54465567
.data = &msm8998_usb3phy_cfg,
5568+
}, {
5569+
.compatible = "qcom,sm6115-qmp-ufs-phy",
5570+
.data = &sm6115_ufsphy_cfg,
54475571
}, {
54485572
.compatible = "qcom,sm8150-qmp-ufs-phy",
54495573
.data = &sm8150_ufsphy_cfg,

‎drivers/phy/qualcomm/phy-qcom-qmp.h

Lines changed: 18 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -191,6 +191,8 @@
191191
#define QSERDES_COM_VCO_TUNE2_MODE0 0x130
192192
#define QSERDES_COM_VCO_TUNE1_MODE1 0x134
193193
#define QSERDES_COM_VCO_TUNE2_MODE1 0x138
194+
#define QSERDES_COM_VCO_TUNE_INITVAL1 0x13c
195+
#define QSERDES_COM_VCO_TUNE_INITVAL2 0x140
194196
#define QSERDES_COM_VCO_TUNE_TIMER1 0x144
195197
#define QSERDES_COM_VCO_TUNE_TIMER2 0x148
196198
#define QSERDES_COM_BG_CTRL 0x170
@@ -220,6 +222,10 @@
220222
/* Only for QMP V2 PHY - RX registers */
221223
#define QSERDES_RX_UCDR_SO_GAIN_HALF 0x010
222224
#define QSERDES_RX_UCDR_SO_GAIN 0x01c
225+
#define QSERDES_RX_UCDR_SVS_SO_GAIN_HALF 0x030
226+
#define QSERDES_RX_UCDR_SVS_SO_GAIN_QUARTER 0x034
227+
#define QSERDES_RX_UCDR_SVS_SO_GAIN_EIGHTH 0x038
228+
#define QSERDES_RX_UCDR_SVS_SO_GAIN 0x03c
223229
#define QSERDES_RX_UCDR_FASTLOCK_FO_GAIN 0x040
224230
#define QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE 0x048
225231
#define QSERDES_RX_RX_TERM_BW 0x090
@@ -243,6 +249,10 @@
243249
#define QPHY_POWER_DOWN_CONTROL 0x04
244250
#define QPHY_TXDEEMPH_M6DB_V0 0x24
245251
#define QPHY_TXDEEMPH_M3P5DB_V0 0x28
252+
#define QPHY_TX_LARGE_AMP_DRV_LVL 0x34
253+
#define QPHY_TX_LARGE_AMP_POST_EMP_LVL 0x38
254+
#define QPHY_TX_SMALL_AMP_DRV_LVL 0x3c
255+
#define QPHY_TX_SMALL_AMP_POST_EMP_LVL 0x40
246256
#define QPHY_ENDPOINT_REFCLK_DRIVE 0x54
247257
#define QPHY_RX_IDLE_DTCT_CNTRL 0x58
248258
#define QPHY_POWER_STATE_CONFIG1 0x60
@@ -253,6 +263,11 @@
253263
#define QPHY_LOCK_DETECT_CONFIG3 0x88
254264
#define QPHY_PWRUP_RESET_DLY_TIME_AUXCLK 0xa0
255265
#define QPHY_LP_WAKEUP_DLY_TIME_AUXCLK 0xa4
266+
#define QPHY_RX_MIN_STALL_NOCONFIG_TIME_CAP 0xcc
267+
#define QPHY_RX_SYM_RESYNC_CTRL 0x13c
268+
#define QPHY_RX_MIN_HIBERN8_TIME 0x140
269+
#define QPHY_RX_SIGDET_CTRL2 0x148
270+
#define QPHY_RX_PWM_GEAR_BAND 0x154
256271
#define QPHY_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB 0x1A8
257272
#define QPHY_OSC_DTCT_ACTIONS 0x1AC
258273
#define QPHY_RX_SIGDET_LVL 0x1D8
@@ -280,6 +295,8 @@
280295
#define QSERDES_V3_COM_SSC_PER2 0x020
281296
#define QSERDES_V3_COM_SSC_STEP_SIZE1 0x024
282297
#define QSERDES_V3_COM_SSC_STEP_SIZE2 0x028
298+
#define QSERDES_V3_COM_POST_DIV 0x02c
299+
#define QSERDES_V3_COM_POST_DIV_MUX 0x030
283300
#define QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN 0x034
284301
# define QSERDES_V3_COM_BIAS_EN 0x0001
285302
# define QSERDES_V3_COM_BIAS_EN_MUX 0x0002
@@ -291,6 +308,7 @@
291308
#define QSERDES_V3_COM_CLK_ENABLE1 0x038
292309
#define QSERDES_V3_COM_SYS_CLK_CTRL 0x03c
293310
#define QSERDES_V3_COM_SYSCLK_BUF_ENABLE 0x040
311+
#define QSERDES_V3_COM_PLL_EN 0x044
294312
#define QSERDES_V3_COM_PLL_IVCO 0x048
295313
#define QSERDES_V3_COM_LOCK_CMP1_MODE0 0x098
296314
#define QSERDES_V3_COM_LOCK_CMP2_MODE0 0x09c

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