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lucasdemarchilucasdemarchi
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drm/i915: Add remaining conversions to GRAPHICS_VER
For some reason coccinelle misses a few cases in header files with calls to INTEL_GEN()/IS_GEN(). Do a manual conversion for those. Signed-off-by: Lucas De Marchi <[email protected]> Reviewed-by: Matt Roper <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
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‎drivers/gpu/drm/i915/i915_drv.h

Lines changed: 18 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -1540,9 +1540,9 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
15401540
(IS_ALDERLAKE_P(__i915) && \
15411541
IS_GT_STEP(__i915, since, until))
15421542

1543-
#define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp)
1544-
#define IS_GEN9_LP(dev_priv) (IS_GEN(dev_priv, 9) && IS_LP(dev_priv))
1545-
#define IS_GEN9_BC(dev_priv) (IS_GEN(dev_priv, 9) && !IS_LP(dev_priv))
1543+
#define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp)
1544+
#define IS_GEN9_LP(dev_priv) (GRAPHICS_VER(dev_priv) == 9 && IS_LP(dev_priv))
1545+
#define IS_GEN9_BC(dev_priv) (GRAPHICS_VER(dev_priv) == 9 && !IS_LP(dev_priv))
15461546

15471547
#define __HAS_ENGINE(engine_mask, id) ((engine_mask) & BIT(id))
15481548
#define HAS_ENGINE(gt, id) __HAS_ENGINE((gt)->info.engine_mask, id)
@@ -1562,12 +1562,12 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
15621562
* The Gen7 cmdparser copies the scanned buffer to the ggtt for execution
15631563
* All later gens can run the final buffer from the ppgtt
15641564
*/
1565-
#define CMDPARSER_USES_GGTT(dev_priv) IS_GEN(dev_priv, 7)
1565+
#define CMDPARSER_USES_GGTT(dev_priv) (GRAPHICS_VER(dev_priv) == 7)
15661566

15671567
#define HAS_LLC(dev_priv) (INTEL_INFO(dev_priv)->has_llc)
15681568
#define HAS_SNOOP(dev_priv) (INTEL_INFO(dev_priv)->has_snoop)
15691569
#define HAS_EDRAM(dev_priv) ((dev_priv)->edram_size_mb)
1570-
#define HAS_SECURE_BATCHES(dev_priv) (INTEL_GEN(dev_priv) < 6)
1570+
#define HAS_SECURE_BATCHES(dev_priv) (GRAPHICS_VER(dev_priv) < 6)
15711571
#define HAS_WT(dev_priv) HAS_EDRAM(dev_priv)
15721572

15731573
#define HWS_NEEDS_PHYSICAL(dev_priv) (INTEL_INFO(dev_priv)->hws_needs_physical)
@@ -1600,31 +1600,30 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
16001600
#define HAS_BROKEN_CS_TLB(dev_priv) (IS_I830(dev_priv) || IS_I845G(dev_priv))
16011601

16021602
#define NEEDS_RC6_CTX_CORRUPTION_WA(dev_priv) \
1603-
(IS_BROADWELL(dev_priv) || IS_GEN(dev_priv, 9))
1603+
(IS_BROADWELL(dev_priv) || GRAPHICS_VER(dev_priv) == 9)
16041604

16051605
/* WaRsDisableCoarsePowerGating:skl,cnl */
16061606
#define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \
16071607
(IS_CANNONLAKE(dev_priv) || \
16081608
IS_SKL_GT3(dev_priv) || \
16091609
IS_SKL_GT4(dev_priv))
16101610

1611-
#define HAS_GMBUS_IRQ(dev_priv) (INTEL_GEN(dev_priv) >= 4)
1612-
#define HAS_GMBUS_BURST_READ(dev_priv) (INTEL_GEN(dev_priv) >= 10 || \
1611+
#define HAS_GMBUS_IRQ(dev_priv) (GRAPHICS_VER(dev_priv) >= 4)
1612+
#define HAS_GMBUS_BURST_READ(dev_priv) (GRAPHICS_VER(dev_priv) >= 10 || \
16131613
IS_GEMINILAKE(dev_priv) || \
16141614
IS_KABYLAKE(dev_priv))
16151615

16161616
/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
16171617
* rows, which changed the alignment requirements and fence programming.
16181618
*/
1619-
#define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN(dev_priv, 2) && \
1620-
!(IS_I915G(dev_priv) || \
1621-
IS_I915GM(dev_priv)))
1619+
#define HAS_128_BYTE_Y_TILING(dev_priv) (GRAPHICS_VER(dev_priv) != 2 && \
1620+
!(IS_I915G(dev_priv) || IS_I915GM(dev_priv)))
16221621
#define SUPPORTS_TV(dev_priv) (INTEL_INFO(dev_priv)->display.supports_tv)
16231622
#define I915_HAS_HOTPLUG(dev_priv) (INTEL_INFO(dev_priv)->display.has_hotplug)
16241623

1625-
#define HAS_FW_BLC(dev_priv) (INTEL_GEN(dev_priv) > 2)
1624+
#define HAS_FW_BLC(dev_priv) (GRAPHICS_VER(dev_priv) > 2)
16261625
#define HAS_FBC(dev_priv) (INTEL_INFO(dev_priv)->display.has_fbc)
1627-
#define HAS_CUR_FBC(dev_priv) (!HAS_GMCH(dev_priv) && INTEL_GEN(dev_priv) >= 7)
1626+
#define HAS_CUR_FBC(dev_priv) (!HAS_GMCH(dev_priv) && GRAPHICS_VER(dev_priv) >= 7)
16281627

16291628
#define HAS_IPS(dev_priv) (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))
16301629

@@ -1635,7 +1634,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
16351634
#define HAS_PSR(dev_priv) (INTEL_INFO(dev_priv)->display.has_psr)
16361635
#define HAS_PSR_HW_TRACKING(dev_priv) \
16371636
(INTEL_INFO(dev_priv)->display.has_psr_hw_tracking)
1638-
#define HAS_PSR2_SEL_FETCH(dev_priv) (INTEL_GEN(dev_priv) >= 12)
1637+
#define HAS_PSR2_SEL_FETCH(dev_priv) (GRAPHICS_VER(dev_priv) >= 12)
16391638
#define HAS_TRANSCODER(dev_priv, trans) ((INTEL_INFO(dev_priv)->cpu_transcoder_mask & BIT(trans)) != 0)
16401639

16411640
#define HAS_RC6(dev_priv) (INTEL_INFO(dev_priv)->has_rc6)
@@ -1646,7 +1645,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
16461645

16471646
#define HAS_DMC(dev_priv) (INTEL_INFO(dev_priv)->display.has_dmc)
16481647

1649-
#define HAS_MSO(i915) (INTEL_GEN(i915) >= 12)
1648+
#define HAS_MSO(i915) (GRAPHICS_VER(i915) >= 12)
16501649

16511650
#define HAS_RUNTIME_PM(dev_priv) (INTEL_INFO(dev_priv)->has_runtime_pm)
16521651
#define HAS_64BIT_RELOC(dev_priv) (INTEL_INFO(dev_priv)->has_64bit_reloc)
@@ -1665,7 +1664,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
16651664

16661665
#define HAS_GMCH(dev_priv) (INTEL_INFO(dev_priv)->display.has_gmch)
16671666

1668-
#define HAS_LSPCON(dev_priv) (IS_GEN_RANGE(dev_priv, 9, 10))
1667+
#define HAS_LSPCON(dev_priv) (IS_GRAPHICS_VER(dev_priv, 9, 10))
16691668

16701669
/* DPF == dynamic parity feature */
16711670
#define HAS_L3_DPF(dev_priv) (INTEL_INFO(dev_priv)->has_l3_dpf)
@@ -1679,7 +1678,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
16791678

16801679
#define HAS_DISPLAY(dev_priv) (INTEL_INFO(dev_priv)->pipe_mask != 0)
16811680

1682-
#define HAS_VRR(i915) (INTEL_GEN(i915) >= 12)
1681+
#define HAS_VRR(i915) (GRAPHICS_VER(i915) >= 12)
16831682

16841683
/* Only valid when HAS_DISPLAY() is true */
16851684
#define INTEL_DISPLAY_ENABLED(dev_priv) \
@@ -1706,7 +1705,7 @@ static inline bool intel_vtd_active(void)
17061705

17071706
static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private *dev_priv)
17081707
{
1709-
return INTEL_GEN(dev_priv) >= 6 && intel_vtd_active();
1708+
return GRAPHICS_VER(dev_priv) >= 6 && intel_vtd_active();
17101709
}
17111710

17121711
static inline bool
@@ -1917,7 +1916,7 @@ int remap_io_sg(struct vm_area_struct *vma,
19171916

19181917
static inline int intel_hws_csb_write_index(struct drm_i915_private *i915)
19191918
{
1920-
if (INTEL_GEN(i915) >= 10)
1919+
if (GRAPHICS_VER(i915) >= 10)
19211920
return CNL_HWS_CSB_WRITE_INDEX;
19221921
else
19231922
return I915_HWS_CSB_WRITE_INDEX;

‎drivers/gpu/drm/i915/i915_reg.h

Lines changed: 13 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -9896,7 +9896,7 @@ enum skl_power_gate {
98969896
#define TRANS_HDCP_CONF(trans) _MMIO_TRANS(trans, _TRANSA_HDCP_CONF, \
98979897
_TRANSB_HDCP_CONF)
98989898
#define HDCP_CONF(dev_priv, trans, port) \
9899-
(INTEL_GEN(dev_priv) >= 12 ? \
9899+
(GRAPHICS_VER(dev_priv) >= 12 ? \
99009900
TRANS_HDCP_CONF(trans) : \
99019901
PORT_HDCP_CONF(port))
99029902

@@ -9909,7 +9909,7 @@ enum skl_power_gate {
99099909
_TRANSA_HDCP_ANINIT, \
99109910
_TRANSB_HDCP_ANINIT)
99119911
#define HDCP_ANINIT(dev_priv, trans, port) \
9912-
(INTEL_GEN(dev_priv) >= 12 ? \
9912+
(GRAPHICS_VER(dev_priv) >= 12 ? \
99139913
TRANS_HDCP_ANINIT(trans) : \
99149914
PORT_HDCP_ANINIT(port))
99159915

@@ -9919,7 +9919,7 @@ enum skl_power_gate {
99199919
#define TRANS_HDCP_ANLO(trans) _MMIO_TRANS(trans, _TRANSA_HDCP_ANLO, \
99209920
_TRANSB_HDCP_ANLO)
99219921
#define HDCP_ANLO(dev_priv, trans, port) \
9922-
(INTEL_GEN(dev_priv) >= 12 ? \
9922+
(GRAPHICS_VER(dev_priv) >= 12 ? \
99239923
TRANS_HDCP_ANLO(trans) : \
99249924
PORT_HDCP_ANLO(port))
99259925

@@ -9929,7 +9929,7 @@ enum skl_power_gate {
99299929
#define TRANS_HDCP_ANHI(trans) _MMIO_TRANS(trans, _TRANSA_HDCP_ANHI, \
99309930
_TRANSB_HDCP_ANHI)
99319931
#define HDCP_ANHI(dev_priv, trans, port) \
9932-
(INTEL_GEN(dev_priv) >= 12 ? \
9932+
(GRAPHICS_VER(dev_priv) >= 12 ? \
99339933
TRANS_HDCP_ANHI(trans) : \
99349934
PORT_HDCP_ANHI(port))
99359935

@@ -9940,7 +9940,7 @@ enum skl_power_gate {
99409940
_TRANSA_HDCP_BKSVLO, \
99419941
_TRANSB_HDCP_BKSVLO)
99429942
#define HDCP_BKSVLO(dev_priv, trans, port) \
9943-
(INTEL_GEN(dev_priv) >= 12 ? \
9943+
(GRAPHICS_VER(dev_priv) >= 12 ? \
99449944
TRANS_HDCP_BKSVLO(trans) : \
99459945
PORT_HDCP_BKSVLO(port))
99469946

@@ -9951,7 +9951,7 @@ enum skl_power_gate {
99519951
_TRANSA_HDCP_BKSVHI, \
99529952
_TRANSB_HDCP_BKSVHI)
99539953
#define HDCP_BKSVHI(dev_priv, trans, port) \
9954-
(INTEL_GEN(dev_priv) >= 12 ? \
9954+
(GRAPHICS_VER(dev_priv) >= 12 ? \
99559955
TRANS_HDCP_BKSVHI(trans) : \
99569956
PORT_HDCP_BKSVHI(port))
99579957

@@ -9962,7 +9962,7 @@ enum skl_power_gate {
99629962
_TRANSA_HDCP_RPRIME, \
99639963
_TRANSB_HDCP_RPRIME)
99649964
#define HDCP_RPRIME(dev_priv, trans, port) \
9965-
(INTEL_GEN(dev_priv) >= 12 ? \
9965+
(GRAPHICS_VER(dev_priv) >= 12 ? \
99669966
TRANS_HDCP_RPRIME(trans) : \
99679967
PORT_HDCP_RPRIME(port))
99689968

@@ -9973,7 +9973,7 @@ enum skl_power_gate {
99739973
_TRANSA_HDCP_STATUS, \
99749974
_TRANSB_HDCP_STATUS)
99759975
#define HDCP_STATUS(dev_priv, trans, port) \
9976-
(INTEL_GEN(dev_priv) >= 12 ? \
9976+
(GRAPHICS_VER(dev_priv) >= 12 ? \
99779977
TRANS_HDCP_STATUS(trans) : \
99789978
PORT_HDCP_STATUS(port))
99799979

@@ -10014,7 +10014,7 @@ enum skl_power_gate {
1001410014
#define AUTH_FORCE_CLR_INPUTCTR BIT(19)
1001510015
#define AUTH_CLR_KEYS BIT(18)
1001610016
#define HDCP2_AUTH(dev_priv, trans, port) \
10017-
(INTEL_GEN(dev_priv) >= 12 ? \
10017+
(GRAPHICS_VER(dev_priv) >= 12 ? \
1001810018
TRANS_HDCP2_AUTH(trans) : \
1001910019
PORT_HDCP2_AUTH(port))
1002010020

@@ -10025,7 +10025,7 @@ enum skl_power_gate {
1002510025
_TRANSB_HDCP2_CTL)
1002610026
#define CTL_LINK_ENCRYPTION_REQ BIT(31)
1002710027
#define HDCP2_CTL(dev_priv, trans, port) \
10028-
(INTEL_GEN(dev_priv) >= 12 ? \
10028+
(GRAPHICS_VER(dev_priv) >= 12 ? \
1002910029
TRANS_HDCP2_CTL(trans) : \
1003010030
PORT_HDCP2_CTL(port))
1003110031

@@ -10039,7 +10039,7 @@ enum skl_power_gate {
1003910039
#define LINK_AUTH_STATUS BIT(21)
1004010040
#define LINK_ENCRYPTION_STATUS BIT(20)
1004110041
#define HDCP2_STATUS(dev_priv, trans, port) \
10042-
(INTEL_GEN(dev_priv) >= 12 ? \
10042+
(GRAPHICS_VER(dev_priv) >= 12 ? \
1004310043
TRANS_HDCP2_STATUS(trans) : \
1004410044
PORT_HDCP2_STATUS(port))
1004510045

@@ -10061,7 +10061,7 @@ enum skl_power_gate {
1006110061
#define STREAM_ENCRYPTION_STATUS BIT(31)
1006210062
#define STREAM_TYPE_STATUS BIT(30)
1006310063
#define HDCP2_STREAM_STATUS(dev_priv, trans, port) \
10064-
(INTEL_GEN(dev_priv) >= 12 ? \
10064+
(GRAPHICS_VER(dev_priv) >= 12 ? \
1006510065
TRANS_HDCP2_STREAM_STATUS(trans) : \
1006610066
PIPE_HDCP2_STREAM_STATUS(pipe))
1006710067

@@ -10077,7 +10077,7 @@ enum skl_power_gate {
1007710077
_TRANSB_HDCP2_AUTH_STREAM)
1007810078
#define AUTH_STREAM_TYPE BIT(31)
1007910079
#define HDCP2_AUTH_STREAM(dev_priv, trans, port) \
10080-
(INTEL_GEN(dev_priv) >= 12 ? \
10080+
(GRAPHICS_VER(dev_priv) >= 12 ? \
1008110081
TRANS_HDCP2_AUTH_STREAM(trans) : \
1008210082
PORT_HDCP2_AUTH_STREAM(port))
1008310083

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