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geertugeertu
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pinctrl: renesas: r8a7790: Add bias pinconf support
Implement support for pull-up (most pins) and pull-down (ASEBRK#/ACK) handling for R-Car H2 and RZ/G1H SoCs, using the common R-Car bias handling. Note that on RZ/G1H, the "ASEBRK#/ACK" pin is called "ACK", but the code doesn't handle that naming difference. Hence users should use the R-Car naming in DTS files. Signed-off-by: Geert Uytterhoeven <[email protected]> Reviewed-by: Niklas Söderlund <[email protected]> Tested-by: Wolfram Sang <[email protected]> Link: https://lore.kernel.org/r/dde6e0b36a4e4494039a3466df208b5ec5c594ee.1619785375.git.geert+renesas@glider.be
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‎drivers/pinctrl/renesas/pfc-r8a7790.c

Lines changed: 294 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -21,18 +21,23 @@
2121
* which case they support both 3.3V and 1.8V signalling.
2222
*/
2323
#define CPU_ALL_GP(fn, sfx) \
24-
PORT_GP_32(0, fn, sfx), \
25-
PORT_GP_30(1, fn, sfx), \
26-
PORT_GP_30(2, fn, sfx), \
27-
PORT_GP_CFG_32(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
28-
PORT_GP_32(4, fn, sfx), \
29-
PORT_GP_32(5, fn, sfx)
24+
PORT_GP_CFG_32(0, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
25+
PORT_GP_CFG_30(1, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
26+
PORT_GP_CFG_30(2, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
27+
PORT_GP_CFG_32(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
28+
PORT_GP_CFG_32(4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
29+
PORT_GP_CFG_32(5, fn, sfx, SH_PFC_PIN_CFG_PULL_UP)
3030

3131
#define CPU_ALL_NOGP(fn) \
32+
PIN_NOGP_CFG(ASEBRK_N_ACK, "ASEBRK#/ACK", fn, SH_PFC_PIN_CFG_PULL_DOWN), \
3233
PIN_NOGP(IIC0_SDA, "AF15", fn), \
3334
PIN_NOGP(IIC0_SCL, "AG15", fn), \
3435
PIN_NOGP(IIC3_SDA, "AH15", fn), \
35-
PIN_NOGP(IIC3_SCL, "AJ15", fn)
36+
PIN_NOGP(IIC3_SCL, "AJ15", fn), \
37+
PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP), \
38+
PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP), \
39+
PIN_NOGP_CFG(TMS, "TMS", fn, SH_PFC_PIN_CFG_PULL_UP), \
40+
PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP)
3641

3742
enum {
3843
PINMUX_RESERVED = 0,
@@ -5992,6 +5997,284 @@ static int r8a7790_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *poc
59925997
return 31 - (pin & 0x1f);
59935998
}
59945999

6000+
static const struct pinmux_bias_reg pinmux_bias_regs[] = {
6001+
{ PINMUX_BIAS_REG("PUPR0", 0xe6060100, "N/A", 0) {
6002+
[ 0] = RCAR_GP_PIN(0, 16), /* A0 */
6003+
[ 1] = RCAR_GP_PIN(0, 17), /* A1 */
6004+
[ 2] = RCAR_GP_PIN(0, 18), /* A2 */
6005+
[ 3] = RCAR_GP_PIN(0, 19), /* A3 */
6006+
[ 4] = RCAR_GP_PIN(0, 20), /* A4 */
6007+
[ 5] = RCAR_GP_PIN(0, 21), /* A5 */
6008+
[ 6] = RCAR_GP_PIN(0, 22), /* A6 */
6009+
[ 7] = RCAR_GP_PIN(0, 23), /* A7 */
6010+
[ 8] = RCAR_GP_PIN(0, 24), /* A8 */
6011+
[ 9] = RCAR_GP_PIN(0, 25), /* A9 */
6012+
[10] = RCAR_GP_PIN(0, 26), /* A10 */
6013+
[11] = RCAR_GP_PIN(0, 27), /* A11 */
6014+
[12] = RCAR_GP_PIN(0, 28), /* A12 */
6015+
[13] = RCAR_GP_PIN(0, 29), /* A13 */
6016+
[14] = RCAR_GP_PIN(0, 30), /* A14 */
6017+
[15] = RCAR_GP_PIN(0, 31), /* A15 */
6018+
[16] = RCAR_GP_PIN(1, 0), /* A16 */
6019+
[17] = RCAR_GP_PIN(1, 1), /* A17 */
6020+
[18] = RCAR_GP_PIN(1, 2), /* A18 */
6021+
[19] = RCAR_GP_PIN(1, 3), /* A19 */
6022+
[20] = RCAR_GP_PIN(1, 4), /* A20 */
6023+
[21] = RCAR_GP_PIN(1, 5), /* A21 */
6024+
[22] = RCAR_GP_PIN(1, 6), /* A22 */
6025+
[23] = RCAR_GP_PIN(1, 7), /* A23 */
6026+
[24] = RCAR_GP_PIN(1, 8), /* A24 */
6027+
[25] = RCAR_GP_PIN(1, 9), /* A25 */
6028+
[26] = RCAR_GP_PIN(1, 12), /* EX_CS0# */
6029+
[27] = RCAR_GP_PIN(1, 13), /* EX_CS1# */
6030+
[28] = RCAR_GP_PIN(1, 14), /* EX_CS2# */
6031+
[29] = RCAR_GP_PIN(1, 15), /* EX_CS3# */
6032+
[30] = RCAR_GP_PIN(1, 16), /* EX_CS4# */
6033+
[31] = RCAR_GP_PIN(1, 17), /* EX_CS5# */
6034+
} },
6035+
{ PINMUX_BIAS_REG("PUPR1", 0xe6060104, "N/A", 0) {
6036+
/* PUPR1 pull-up pins */
6037+
[ 0] = RCAR_GP_PIN(1, 18), /* BS# */
6038+
[ 1] = RCAR_GP_PIN(1, 19), /* RD# */
6039+
[ 2] = RCAR_GP_PIN(1, 20), /* RD/WR# */
6040+
[ 3] = RCAR_GP_PIN(1, 21), /* WE0# */
6041+
[ 4] = RCAR_GP_PIN(1, 22), /* WE1# */
6042+
[ 5] = RCAR_GP_PIN(1, 23), /* EX_WAIT0 */
6043+
[ 6] = RCAR_GP_PIN(5, 24), /* AVS1 */
6044+
[ 7] = RCAR_GP_PIN(5, 25), /* AVS2 */
6045+
[ 8] = RCAR_GP_PIN(1, 10), /* CS0# */
6046+
[ 9] = RCAR_GP_PIN(1, 11), /* CS1#/A26 */
6047+
[10] = PIN_TRST_N, /* TRST# */
6048+
[11] = PIN_TCK, /* TCK */
6049+
[12] = PIN_TMS, /* TMS */
6050+
[13] = PIN_TDI, /* TDI */
6051+
[14] = SH_PFC_PIN_NONE,
6052+
[15] = SH_PFC_PIN_NONE,
6053+
[16] = RCAR_GP_PIN(0, 0), /* D0 */
6054+
[17] = RCAR_GP_PIN(0, 1), /* D1 */
6055+
[18] = RCAR_GP_PIN(0, 2), /* D2 */
6056+
[19] = RCAR_GP_PIN(0, 3), /* D3 */
6057+
[20] = RCAR_GP_PIN(0, 4), /* D4 */
6058+
[21] = RCAR_GP_PIN(0, 5), /* D5 */
6059+
[22] = RCAR_GP_PIN(0, 6), /* D6 */
6060+
[23] = RCAR_GP_PIN(0, 7), /* D7 */
6061+
[24] = RCAR_GP_PIN(0, 8), /* D8 */
6062+
[25] = RCAR_GP_PIN(0, 9), /* D9 */
6063+
[26] = RCAR_GP_PIN(0, 10), /* D10 */
6064+
[27] = RCAR_GP_PIN(0, 11), /* D11 */
6065+
[28] = RCAR_GP_PIN(0, 12), /* D12 */
6066+
[29] = RCAR_GP_PIN(0, 13), /* D13 */
6067+
[30] = RCAR_GP_PIN(0, 14), /* D14 */
6068+
[31] = RCAR_GP_PIN(0, 15), /* D15 */
6069+
} },
6070+
{ PINMUX_BIAS_REG("N/A", 0, "PUPR1", 0xe6060104) {
6071+
/* PUPR1 pull-down pins */
6072+
[ 0] = SH_PFC_PIN_NONE,
6073+
[ 1] = SH_PFC_PIN_NONE,
6074+
[ 2] = SH_PFC_PIN_NONE,
6075+
[ 3] = SH_PFC_PIN_NONE,
6076+
[ 4] = SH_PFC_PIN_NONE,
6077+
[ 5] = SH_PFC_PIN_NONE,
6078+
[ 6] = SH_PFC_PIN_NONE,
6079+
[ 7] = SH_PFC_PIN_NONE,
6080+
[ 8] = SH_PFC_PIN_NONE,
6081+
[ 9] = SH_PFC_PIN_NONE,
6082+
[10] = SH_PFC_PIN_NONE,
6083+
[11] = SH_PFC_PIN_NONE,
6084+
[12] = SH_PFC_PIN_NONE,
6085+
[13] = SH_PFC_PIN_NONE,
6086+
[14] = SH_PFC_PIN_NONE,
6087+
[15] = PIN_ASEBRK_N_ACK, /* ASEBRK#/ACK */
6088+
[16] = SH_PFC_PIN_NONE,
6089+
[17] = SH_PFC_PIN_NONE,
6090+
[18] = SH_PFC_PIN_NONE,
6091+
[19] = SH_PFC_PIN_NONE,
6092+
[20] = SH_PFC_PIN_NONE,
6093+
[21] = SH_PFC_PIN_NONE,
6094+
[22] = SH_PFC_PIN_NONE,
6095+
[23] = SH_PFC_PIN_NONE,
6096+
[24] = SH_PFC_PIN_NONE,
6097+
[25] = SH_PFC_PIN_NONE,
6098+
[26] = SH_PFC_PIN_NONE,
6099+
[27] = SH_PFC_PIN_NONE,
6100+
[28] = SH_PFC_PIN_NONE,
6101+
[29] = SH_PFC_PIN_NONE,
6102+
[30] = SH_PFC_PIN_NONE,
6103+
[31] = SH_PFC_PIN_NONE,
6104+
} },
6105+
{ PINMUX_BIAS_REG("PUPR2", 0xe6060108, "N/A", 0) {
6106+
[ 0] = RCAR_GP_PIN(5, 28), /* DU_DOTCLKIN2 */
6107+
[ 1] = SH_PFC_PIN_NONE,
6108+
[ 2] = SH_PFC_PIN_NONE,
6109+
[ 3] = SH_PFC_PIN_NONE,
6110+
[ 4] = SH_PFC_PIN_NONE,
6111+
[ 5] = RCAR_GP_PIN(2, 0), /* VI0_CLK */
6112+
[ 6] = RCAR_GP_PIN(2, 1), /* VI0_DATA0_VI0_B0 */
6113+
[ 7] = RCAR_GP_PIN(2, 2), /* VI0_DATA1_VI0_B1 */
6114+
[ 8] = RCAR_GP_PIN(2, 3), /* VI0_DATA2_VI0_B2 */
6115+
[ 9] = RCAR_GP_PIN(2, 4), /* VI0_DATA3_VI0_B3 */
6116+
[10] = RCAR_GP_PIN(2, 5), /* VI0_DATA4_VI0_B4 */
6117+
[11] = RCAR_GP_PIN(2, 6), /* VI0_DATA5_VI0_B5 */
6118+
[12] = RCAR_GP_PIN(2, 7), /* VI0_DATA6_VI0_B6 */
6119+
[13] = RCAR_GP_PIN(2, 8), /* VI0_DATA7_VI0_B7 */
6120+
[14] = RCAR_GP_PIN(2, 9), /* VI1_CLK */
6121+
[15] = RCAR_GP_PIN(2, 10), /* VI1_DATA0_VI1_B0 */
6122+
[16] = RCAR_GP_PIN(2, 11), /* VI1_DATA1_VI1_B1 */
6123+
[17] = RCAR_GP_PIN(2, 12), /* VI1_DATA2_VI1_B2 */
6124+
[18] = RCAR_GP_PIN(2, 13), /* VI1_DATA3_VI1_B3 */
6125+
[19] = RCAR_GP_PIN(2, 14), /* VI1_DATA4_VI1_B4 */
6126+
[20] = RCAR_GP_PIN(2, 15), /* VI1_DATA5_VI1_B5 */
6127+
[21] = RCAR_GP_PIN(2, 16), /* VI1_DATA6_VI1_B6 */
6128+
[22] = RCAR_GP_PIN(2, 17), /* VI1_DATA7_VI1_B7 */
6129+
[23] = RCAR_GP_PIN(5, 27), /* DU_DOTCLKIN1 */
6130+
[24] = SH_PFC_PIN_NONE,
6131+
[25] = SH_PFC_PIN_NONE,
6132+
[26] = SH_PFC_PIN_NONE,
6133+
[27] = RCAR_GP_PIN(4, 0), /* MLB_CLK */
6134+
[28] = RCAR_GP_PIN(4, 1), /* MLB_SIG */
6135+
[29] = RCAR_GP_PIN(4, 2), /* MLB_DAT */
6136+
[30] = SH_PFC_PIN_NONE,
6137+
[31] = RCAR_GP_PIN(5, 26), /* DU_DOTCLKIN0 */
6138+
} },
6139+
{ PINMUX_BIAS_REG("PUPR3", 0xe606010c, "N/A", 0) {
6140+
[ 0] = RCAR_GP_PIN(3, 0), /* SD0_CLK */
6141+
[ 1] = RCAR_GP_PIN(3, 1), /* SD0_CMD */
6142+
[ 2] = RCAR_GP_PIN(3, 2), /* SD0_DAT0 */
6143+
[ 3] = RCAR_GP_PIN(3, 3), /* SD0_DAT1 */
6144+
[ 4] = RCAR_GP_PIN(3, 4), /* SD0_DAT2 */
6145+
[ 5] = RCAR_GP_PIN(3, 5), /* SD0_DAT3 */
6146+
[ 6] = RCAR_GP_PIN(3, 6), /* SD0_CD */
6147+
[ 7] = RCAR_GP_PIN(3, 7), /* SD0_WP */
6148+
[ 8] = RCAR_GP_PIN(3, 8), /* SD1_CLK */
6149+
[ 9] = RCAR_GP_PIN(3, 9), /* SD1_CMD */
6150+
[10] = RCAR_GP_PIN(3, 10), /* SD1_DAT0 */
6151+
[11] = RCAR_GP_PIN(3, 11), /* SD1_DAT1 */
6152+
[12] = RCAR_GP_PIN(3, 12), /* SD1_DAT2 */
6153+
[13] = RCAR_GP_PIN(3, 13), /* SD1_DAT3 */
6154+
[14] = RCAR_GP_PIN(3, 14), /* SD1_CD */
6155+
[15] = RCAR_GP_PIN(3, 15), /* SD1_WP */
6156+
[16] = RCAR_GP_PIN(3, 16), /* SD2_CLK */
6157+
[17] = RCAR_GP_PIN(3, 17), /* SD2_CMD */
6158+
[18] = RCAR_GP_PIN(3, 18), /* SD2_DAT0 */
6159+
[19] = RCAR_GP_PIN(3, 19), /* SD2_DAT1 */
6160+
[20] = RCAR_GP_PIN(3, 20), /* SD2_DAT2 */
6161+
[21] = RCAR_GP_PIN(3, 21), /* SD2_DAT3 */
6162+
[22] = RCAR_GP_PIN(3, 22), /* SD2_CD */
6163+
[23] = RCAR_GP_PIN(3, 23), /* SD2_WP */
6164+
[24] = RCAR_GP_PIN(3, 24), /* SD3_CLK */
6165+
[25] = RCAR_GP_PIN(3, 25), /* SD3_CMD */
6166+
[26] = RCAR_GP_PIN(3, 26), /* SD3_DAT0 */
6167+
[27] = RCAR_GP_PIN(3, 27), /* SD3_DAT1 */
6168+
[28] = RCAR_GP_PIN(3, 28), /* SD3_DAT2 */
6169+
[29] = RCAR_GP_PIN(3, 29), /* SD3_DAT3 */
6170+
[30] = RCAR_GP_PIN(3, 30), /* SD3_CD */
6171+
[31] = RCAR_GP_PIN(3, 31), /* SD3_WP */
6172+
} },
6173+
{ PINMUX_BIAS_REG("PUPR4", 0xe6060110, "N/A", 0) {
6174+
[ 0] = RCAR_GP_PIN(4, 3), /* SSI_SCK0129 */
6175+
[ 1] = RCAR_GP_PIN(4, 4), /* SSI_WS0129 */
6176+
[ 2] = RCAR_GP_PIN(4, 5), /* SSI_SDATA0 */
6177+
[ 3] = RCAR_GP_PIN(4, 6), /* SSI_SDATA1 */
6178+
[ 4] = RCAR_GP_PIN(4, 7), /* SSI_SDATA2 */
6179+
[ 5] = RCAR_GP_PIN(4, 8), /* SSI_SCK34 */
6180+
[ 6] = RCAR_GP_PIN(4, 9), /* SSI_WS34 */
6181+
[ 7] = RCAR_GP_PIN(4, 10), /* SSI_SDATA3 */
6182+
[ 8] = RCAR_GP_PIN(4, 11), /* SSI_SCK4 */
6183+
[ 9] = RCAR_GP_PIN(4, 12), /* SSI_WS4 */
6184+
[10] = RCAR_GP_PIN(4, 13), /* SSI_SDATA4 */
6185+
[11] = RCAR_GP_PIN(4, 14), /* SSI_SCK5 */
6186+
[12] = RCAR_GP_PIN(4, 15), /* SSI_WS5 */
6187+
[13] = RCAR_GP_PIN(4, 16), /* SSI_SDATA5 */
6188+
[14] = RCAR_GP_PIN(4, 17), /* SSI_SCK6 */
6189+
[15] = RCAR_GP_PIN(4, 18), /* SSI_WS6 */
6190+
[16] = RCAR_GP_PIN(4, 19), /* SSI_SDATA6 */
6191+
[17] = RCAR_GP_PIN(4, 20), /* SSI_SCK78 */
6192+
[18] = RCAR_GP_PIN(4, 21), /* SSI_WS78 */
6193+
[19] = RCAR_GP_PIN(4, 22), /* SSI_SDATA7 */
6194+
[20] = RCAR_GP_PIN(4, 23), /* SSI_SDATA8 */
6195+
[21] = RCAR_GP_PIN(4, 24), /* SSI_SDATA9 */
6196+
[22] = RCAR_GP_PIN(4, 25), /* AUDIO_CLKA */
6197+
[23] = RCAR_GP_PIN(4, 26), /* AUDIO_CLKB */
6198+
[24] = RCAR_GP_PIN(1, 24), /* DREQ0 */
6199+
[25] = RCAR_GP_PIN(1, 25), /* DACK0 */
6200+
[26] = RCAR_GP_PIN(1, 26), /* DREQ1 */
6201+
[27] = RCAR_GP_PIN(1, 27), /* DACK1 */
6202+
[28] = RCAR_GP_PIN(1, 28), /* DREQ2 */
6203+
[29] = RCAR_GP_PIN(1, 29), /* DACK2 */
6204+
[30] = RCAR_GP_PIN(2, 18), /* ETH_CRS_DV */
6205+
[31] = RCAR_GP_PIN(2, 19), /* ETH_RX_ER */
6206+
} },
6207+
{ PINMUX_BIAS_REG("PUPR5", 0xe6060114, "N/A", 0) {
6208+
[ 0] = RCAR_GP_PIN(4, 27), /* SCIFA0_SCK */
6209+
[ 1] = RCAR_GP_PIN(4, 28), /* SCIFA0_RXD */
6210+
[ 2] = RCAR_GP_PIN(4, 29), /* SCIFA0_TXD */
6211+
[ 3] = RCAR_GP_PIN(4, 30), /* SCIFA0_CTS# */
6212+
[ 4] = RCAR_GP_PIN(4, 31), /* SCIFA0_RTS# */
6213+
[ 5] = RCAR_GP_PIN(5, 0), /* SCIFA1_RXD */
6214+
[ 6] = RCAR_GP_PIN(5, 1), /* SCIFA1_TXD */
6215+
[ 7] = RCAR_GP_PIN(5, 2), /* SCIFA1_CTS# */
6216+
[ 8] = RCAR_GP_PIN(5, 3), /* SCIFA1_RTS# */
6217+
[ 9] = RCAR_GP_PIN(5, 4), /* SCIFA2_SCK */
6218+
[10] = RCAR_GP_PIN(5, 5), /* SCIFA2_RXD */
6219+
[11] = RCAR_GP_PIN(5, 6), /* SCIFA2_TXD */
6220+
[12] = RCAR_GP_PIN(5, 7), /* HSCK0 */
6221+
[13] = RCAR_GP_PIN(5, 8), /* HRX0 */
6222+
[14] = RCAR_GP_PIN(5, 9), /* HTX0 */
6223+
[15] = RCAR_GP_PIN(5, 10), /* HCTS0# */
6224+
[16] = RCAR_GP_PIN(5, 11), /* HRTS0# */
6225+
[17] = RCAR_GP_PIN(5, 12), /* MSIOF0_SCK */
6226+
[18] = RCAR_GP_PIN(5, 13), /* MSIOF0_SYNC */
6227+
[19] = RCAR_GP_PIN(5, 14), /* MSIOF0_SS1 */
6228+
[20] = RCAR_GP_PIN(5, 15), /* MSIOF0_TXD */
6229+
[21] = RCAR_GP_PIN(5, 16), /* MSIOF0_SS2 */
6230+
[22] = RCAR_GP_PIN(5, 17), /* MSIOF0_RXD */
6231+
[23] = RCAR_GP_PIN(5, 18), /* USB0_PWEN */
6232+
[24] = RCAR_GP_PIN(5, 19), /* USB0_OVC_VBUS */
6233+
[25] = RCAR_GP_PIN(5, 20), /* USB1_PWEN */
6234+
[26] = RCAR_GP_PIN(5, 21), /* USB1_OVC */
6235+
[27] = RCAR_GP_PIN(5, 22), /* USB2_PWEN */
6236+
[28] = RCAR_GP_PIN(5, 23), /* USB2_OVC */
6237+
[29] = RCAR_GP_PIN(2, 20), /* ETH_RXD0 */
6238+
[30] = RCAR_GP_PIN(2, 21), /* ETH_RXD1 */
6239+
[31] = RCAR_GP_PIN(2, 22), /* ETH_LINK */
6240+
} },
6241+
{ PINMUX_BIAS_REG("PUPR6", 0xe6060118, "N/A", 0) {
6242+
[ 0] = RCAR_GP_PIN(2, 23), /* ETH_REF_CLK */
6243+
[ 1] = RCAR_GP_PIN(2, 24), /* ETH_MDIO */
6244+
[ 2] = RCAR_GP_PIN(2, 25), /* ETH_TXD1 */
6245+
[ 3] = RCAR_GP_PIN(2, 26), /* ETH_TX_EN */
6246+
[ 4] = RCAR_GP_PIN(2, 27), /* ETH_MAGIC */
6247+
[ 5] = RCAR_GP_PIN(2, 28), /* ETH_TXD0 */
6248+
[ 6] = RCAR_GP_PIN(2, 29), /* ETH_MDC */
6249+
[ 7] = RCAR_GP_PIN(5, 29), /* PWM0 */
6250+
[ 8] = RCAR_GP_PIN(5, 30), /* PWM1 */
6251+
[ 9] = RCAR_GP_PIN(5, 31), /* PWM2 */
6252+
[10] = SH_PFC_PIN_NONE,
6253+
[11] = SH_PFC_PIN_NONE,
6254+
[12] = SH_PFC_PIN_NONE,
6255+
[13] = SH_PFC_PIN_NONE,
6256+
[14] = SH_PFC_PIN_NONE,
6257+
[15] = SH_PFC_PIN_NONE,
6258+
[16] = SH_PFC_PIN_NONE,
6259+
[17] = SH_PFC_PIN_NONE,
6260+
[18] = SH_PFC_PIN_NONE,
6261+
[19] = SH_PFC_PIN_NONE,
6262+
[20] = SH_PFC_PIN_NONE,
6263+
[21] = SH_PFC_PIN_NONE,
6264+
[22] = SH_PFC_PIN_NONE,
6265+
[23] = SH_PFC_PIN_NONE,
6266+
[24] = SH_PFC_PIN_NONE,
6267+
[25] = SH_PFC_PIN_NONE,
6268+
[26] = SH_PFC_PIN_NONE,
6269+
[27] = SH_PFC_PIN_NONE,
6270+
[28] = SH_PFC_PIN_NONE,
6271+
[29] = SH_PFC_PIN_NONE,
6272+
[30] = SH_PFC_PIN_NONE,
6273+
[31] = SH_PFC_PIN_NONE,
6274+
} },
6275+
{ /* sentinel */ }
6276+
};
6277+
59956278
static const struct soc_device_attribute r8a7790_tdsel[] = {
59966279
{ .soc_id = "r8a7790", .revision = "ES1.0" },
59976280
{ /* sentinel */ }
@@ -6009,6 +6292,8 @@ static int r8a7790_pinmux_soc_init(struct sh_pfc *pfc)
60096292
static const struct sh_pfc_soc_operations r8a7790_pinmux_ops = {
60106293
.init = r8a7790_pinmux_soc_init,
60116294
.pin_to_pocctrl = r8a7790_pin_to_pocctrl,
6295+
.get_bias = rcar_pinmux_get_bias,
6296+
.set_bias = rcar_pinmux_set_bias,
60126297
};
60136298

60146299
#ifdef CONFIG_PINCTRL_PFC_R8A7742
@@ -6027,6 +6312,7 @@ const struct sh_pfc_soc_info r8a7742_pinmux_info = {
60276312
.nr_functions = ARRAY_SIZE(pinmux_functions.common),
60286313

60296314
.cfg_regs = pinmux_config_regs,
6315+
.bias_regs = pinmux_bias_regs,
60306316

60316317
.pinmux_data = pinmux_data,
60326318
.pinmux_data_size = ARRAY_SIZE(pinmux_data),
@@ -6051,6 +6337,7 @@ const struct sh_pfc_soc_info r8a7790_pinmux_info = {
60516337
ARRAY_SIZE(pinmux_functions.automotive),
60526338

60536339
.cfg_regs = pinmux_config_regs,
6340+
.bias_regs = pinmux_bias_regs,
60546341

60556342
.pinmux_data = pinmux_data,
60566343
.pinmux_data_size = ARRAY_SIZE(pinmux_data),

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