@@ -519,7 +519,7 @@ static long lmk04832_vco_round_rate(struct clk_hw *hw, unsigned long rate,
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vco_rate = lmk04832_calc_pll2_params (* prate , rate , & n , & p , & r );
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if (vco_rate < 0 ) {
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- dev_err (lmk -> dev , "PLL2 parmeters out of range\n" );
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+ dev_err (lmk -> dev , "PLL2 parameters out of range\n" );
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return vco_rate ;
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}
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@@ -550,7 +550,7 @@ static int lmk04832_vco_set_rate(struct clk_hw *hw, unsigned long rate,
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vco_rate = lmk04832_calc_pll2_params (prate , rate , & n , & p , & r );
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if (vco_rate < 0 ) {
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- dev_err (lmk -> dev , "failed to determine PLL2 parmeters \n" );
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+ dev_err (lmk -> dev , "failed to determine PLL2 parameters \n" );
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return vco_rate ;
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}
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@@ -573,7 +573,7 @@ static int lmk04832_vco_set_rate(struct clk_hw *hw, unsigned long rate,
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/*
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* PLL2_N registers must be programmed after other PLL2 dividers are
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- * programed to ensure proper VCO frequency calibration
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+ * programmed to ensure proper VCO frequency calibration
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*/
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ret = regmap_write (lmk -> regmap , LMK04832_REG_PLL2_N_0 ,
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FIELD_GET (0x030000 , n ));
@@ -1120,7 +1120,7 @@ static int lmk04832_dclk_set_rate(struct clk_hw *hw, unsigned long rate,
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return - EINVAL ;
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}
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- /* Enable Duty Cycle Corretion */
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+ /* Enable Duty Cycle Correction */
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if (dclk_div == 1 ) {
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ret = regmap_update_bits (lmk -> regmap ,
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LMK04832_REG_CLKOUT_CTRL3 (dclk -> id ),
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