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linuswlinusw
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Merge tag 'renesas-pinctrl-for-v5.14-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel
pinctrl: renesas: Updates for v5.14 (take two) - Add bias support for the R-Car H2, V2H, E2, V3M, and V3H, and RZ/G1C, RZ/G1H, and RZ/G1E SoCs.
2 parents ee9889d + c3975a7 commit 2f792ec

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6 files changed

+1844
-80
lines changed

6 files changed

+1844
-80
lines changed

‎drivers/pinctrl/renesas/pfc-r8a77470.c

Lines changed: 306 additions & 40 deletions
Original file line numberDiff line numberDiff line change
@@ -11,46 +11,56 @@
1111
#include "sh_pfc.h"
1212

1313
#define CPU_ALL_GP(fn, sfx) \
14-
PORT_GP_4(0, fn, sfx), \
15-
PORT_GP_1(0, 4, fn, sfx), \
16-
PORT_GP_CFG_1(0, 5, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
17-
PORT_GP_CFG_1(0, 6, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
18-
PORT_GP_CFG_1(0, 7, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
19-
PORT_GP_CFG_1(0, 8, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
20-
PORT_GP_CFG_1(0, 9, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
21-
PORT_GP_CFG_1(0, 10, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
22-
PORT_GP_1(0, 11, fn, sfx), \
23-
PORT_GP_1(0, 12, fn, sfx), \
24-
PORT_GP_CFG_1(0, 13, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
25-
PORT_GP_CFG_1(0, 14, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
26-
PORT_GP_CFG_1(0, 15, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
27-
PORT_GP_CFG_1(0, 16, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
28-
PORT_GP_CFG_1(0, 17, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
29-
PORT_GP_CFG_1(0, 18, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
30-
PORT_GP_CFG_1(0, 19, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
31-
PORT_GP_CFG_1(0, 20, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
32-
PORT_GP_CFG_1(0, 21, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
33-
PORT_GP_CFG_1(0, 22, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
34-
PORT_GP_23(1, fn, sfx), \
35-
PORT_GP_32(2, fn, sfx), \
36-
PORT_GP_17(3, fn, sfx), \
37-
PORT_GP_1(3, 27, fn, sfx), \
38-
PORT_GP_1(3, 28, fn, sfx), \
39-
PORT_GP_1(3, 29, fn, sfx), \
40-
PORT_GP_14(4, fn, sfx), \
41-
PORT_GP_CFG_1(4, 14, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
42-
PORT_GP_CFG_1(4, 15, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
43-
PORT_GP_CFG_1(4, 16, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
44-
PORT_GP_CFG_1(4, 17, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
45-
PORT_GP_CFG_1(4, 18, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
46-
PORT_GP_CFG_1(4, 19, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
47-
PORT_GP_1(4, 20, fn, sfx), \
48-
PORT_GP_1(4, 21, fn, sfx), \
49-
PORT_GP_1(4, 22, fn, sfx), \
50-
PORT_GP_1(4, 23, fn, sfx), \
51-
PORT_GP_1(4, 24, fn, sfx), \
52-
PORT_GP_1(4, 25, fn, sfx), \
53-
PORT_GP_32(5, fn, sfx)
14+
PORT_GP_CFG_4(0, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
15+
PORT_GP_CFG_1(0, 4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
16+
PORT_GP_CFG_1(0, 5, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
17+
PORT_GP_CFG_1(0, 6, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
18+
PORT_GP_CFG_1(0, 7, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
19+
PORT_GP_CFG_1(0, 8, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
20+
PORT_GP_CFG_1(0, 9, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
21+
PORT_GP_CFG_1(0, 10, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
22+
PORT_GP_CFG_1(0, 11, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
23+
PORT_GP_CFG_1(0, 12, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
24+
PORT_GP_CFG_1(0, 13, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
25+
PORT_GP_CFG_1(0, 14, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
26+
PORT_GP_CFG_1(0, 15, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
27+
PORT_GP_CFG_1(0, 16, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
28+
PORT_GP_CFG_1(0, 17, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
29+
PORT_GP_CFG_1(0, 18, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
30+
PORT_GP_CFG_1(0, 19, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
31+
PORT_GP_CFG_1(0, 20, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
32+
PORT_GP_CFG_1(0, 21, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
33+
PORT_GP_CFG_1(0, 22, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
34+
PORT_GP_CFG_23(1, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
35+
PORT_GP_CFG_32(2, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
36+
PORT_GP_CFG_17(3, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
37+
PORT_GP_CFG_1(3, 27, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
38+
PORT_GP_CFG_1(3, 28, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
39+
PORT_GP_CFG_1(3, 29, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
40+
PORT_GP_CFG_14(4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
41+
PORT_GP_CFG_1(4, 14, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
42+
PORT_GP_CFG_1(4, 15, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
43+
PORT_GP_CFG_1(4, 16, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
44+
PORT_GP_CFG_1(4, 17, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
45+
PORT_GP_CFG_1(4, 18, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
46+
PORT_GP_CFG_1(4, 19, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
47+
PORT_GP_CFG_1(4, 20, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
48+
PORT_GP_CFG_1(4, 21, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
49+
PORT_GP_CFG_1(4, 22, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
50+
PORT_GP_CFG_1(4, 23, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
51+
PORT_GP_CFG_1(4, 24, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
52+
PORT_GP_CFG_1(4, 25, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
53+
PORT_GP_CFG_32(5, fn, sfx, SH_PFC_PIN_CFG_PULL_UP)
54+
55+
#define CPU_ALL_NOGP(fn) \
56+
PIN_NOGP_CFG(ASEBRK_N_ACK, "ASEBRK#/ACK", fn, SH_PFC_PIN_CFG_PULL_DOWN), \
57+
PIN_NOGP_CFG(NMI, "NMI", fn, SH_PFC_PIN_CFG_PULL_UP), \
58+
PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, SH_PFC_PIN_CFG_PULL_UP), \
59+
PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP), \
60+
PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP), \
61+
PIN_NOGP_CFG(TDO, "TDO", fn, SH_PFC_PIN_CFG_PULL_UP), \
62+
PIN_NOGP_CFG(TMS, "TMS", fn, SH_PFC_PIN_CFG_PULL_UP), \
63+
PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP)
5464

5565
enum {
5666
PINMUX_RESERVED = 0,
@@ -1121,8 +1131,17 @@ static const u16 pinmux_data[] = {
11211131
PINMUX_IPSR_GPSR(IP17_27_24, VI0_VSYNC_N),
11221132
};
11231133

1134+
/*
1135+
* Pins not associated with a GPIO port.
1136+
*/
1137+
enum {
1138+
GP_ASSIGN_LAST(),
1139+
NOGP_ALL(),
1140+
};
1141+
11241142
static const struct sh_pfc_pin pinmux_pins[] = {
11251143
PINMUX_GPIO_GP_ALL(),
1144+
PINMUX_NOGP_ALL(),
11261145
};
11271146

11281147
/* - AVB -------------------------------------------------------------------- */
@@ -3420,8 +3439,254 @@ static int r8a77470_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin,
34203439
return bit;
34213440
}
34223441

3442+
static const struct pinmux_bias_reg pinmux_bias_regs[] = {
3443+
{ PINMUX_BIAS_REG("PUPR0", 0xe6060100, "N/A", 0) {
3444+
/* PUPR0 pull-up pins */
3445+
[ 0] = RCAR_GP_PIN(1, 0), /* D0 */
3446+
[ 1] = RCAR_GP_PIN(0, 22), /* MMC0_D7 */
3447+
[ 2] = RCAR_GP_PIN(0, 21), /* MMC0_D6 */
3448+
[ 3] = RCAR_GP_PIN(0, 20), /* MMC0_D5 */
3449+
[ 4] = RCAR_GP_PIN(0, 19), /* MMC0_D4 */
3450+
[ 5] = RCAR_GP_PIN(0, 18), /* MMC0_D3 */
3451+
[ 6] = RCAR_GP_PIN(0, 17), /* MMC0_D2 */
3452+
[ 7] = RCAR_GP_PIN(0, 16), /* MMC0_D1 */
3453+
[ 8] = RCAR_GP_PIN(0, 15), /* MMC0_D0 */
3454+
[ 9] = RCAR_GP_PIN(0, 14), /* MMC0_CMD */
3455+
[10] = RCAR_GP_PIN(0, 13), /* MMC0_CLK */
3456+
[11] = RCAR_GP_PIN(0, 12), /* SD0_WP */
3457+
[12] = RCAR_GP_PIN(0, 11), /* SD0_CD */
3458+
[13] = RCAR_GP_PIN(0, 10), /* SD0_DAT3 */
3459+
[14] = RCAR_GP_PIN(0, 9), /* SD0_DAT2 */
3460+
[15] = RCAR_GP_PIN(0, 8), /* SD0_DAT1 */
3461+
[16] = RCAR_GP_PIN(0, 7), /* SD0_DAT0 */
3462+
[17] = RCAR_GP_PIN(0, 6), /* SD0_CMD */
3463+
[18] = RCAR_GP_PIN(0, 5), /* SD0_CLK */
3464+
[19] = RCAR_GP_PIN(0, 4), /* CLKOUT */
3465+
[20] = PIN_NMI, /* NMI */
3466+
[21] = RCAR_GP_PIN(0, 3), /* USB1_OVC */
3467+
[22] = RCAR_GP_PIN(0, 2), /* USB1_PWEN */
3468+
[23] = RCAR_GP_PIN(0, 1), /* USB0_OVC */
3469+
[24] = RCAR_GP_PIN(0, 0), /* USB0_PWEN */
3470+
[25] = SH_PFC_PIN_NONE,
3471+
[26] = PIN_TDO, /* TDO */
3472+
[27] = PIN_TDI, /* TDI */
3473+
[28] = PIN_TMS, /* TMS */
3474+
[29] = PIN_TCK, /* TCK */
3475+
[30] = PIN_TRST_N, /* TRST# */
3476+
[31] = PIN_PRESETOUT_N, /* PRESETOUT# */
3477+
} },
3478+
{ PINMUX_BIAS_REG("N/A", 0, "PUPR0", 0xe6060100) {
3479+
/* PUPR0 pull-down pins */
3480+
[ 0] = SH_PFC_PIN_NONE,
3481+
[ 1] = SH_PFC_PIN_NONE,
3482+
[ 2] = SH_PFC_PIN_NONE,
3483+
[ 3] = SH_PFC_PIN_NONE,
3484+
[ 4] = SH_PFC_PIN_NONE,
3485+
[ 5] = SH_PFC_PIN_NONE,
3486+
[ 6] = SH_PFC_PIN_NONE,
3487+
[ 7] = SH_PFC_PIN_NONE,
3488+
[ 8] = SH_PFC_PIN_NONE,
3489+
[ 9] = SH_PFC_PIN_NONE,
3490+
[10] = SH_PFC_PIN_NONE,
3491+
[11] = SH_PFC_PIN_NONE,
3492+
[12] = SH_PFC_PIN_NONE,
3493+
[13] = SH_PFC_PIN_NONE,
3494+
[14] = SH_PFC_PIN_NONE,
3495+
[15] = SH_PFC_PIN_NONE,
3496+
[16] = SH_PFC_PIN_NONE,
3497+
[17] = SH_PFC_PIN_NONE,
3498+
[18] = SH_PFC_PIN_NONE,
3499+
[19] = SH_PFC_PIN_NONE,
3500+
[20] = SH_PFC_PIN_NONE,
3501+
[21] = SH_PFC_PIN_NONE,
3502+
[22] = SH_PFC_PIN_NONE,
3503+
[23] = SH_PFC_PIN_NONE,
3504+
[24] = SH_PFC_PIN_NONE,
3505+
[25] = PIN_ASEBRK_N_ACK, /* ASEBRK#/ACK */
3506+
[26] = SH_PFC_PIN_NONE,
3507+
[27] = SH_PFC_PIN_NONE,
3508+
[28] = SH_PFC_PIN_NONE,
3509+
[29] = SH_PFC_PIN_NONE,
3510+
[30] = SH_PFC_PIN_NONE,
3511+
[31] = SH_PFC_PIN_NONE,
3512+
} },
3513+
{ PINMUX_BIAS_REG("PUPR1", 0xe6060104, "N/A", 0) {
3514+
[ 0] = RCAR_GP_PIN(2, 9), /* DU0_DG1 */
3515+
[ 1] = RCAR_GP_PIN(2, 8), /* DU0_DG0 */
3516+
[ 2] = RCAR_GP_PIN(2, 7), /* DU0_DR7 */
3517+
[ 3] = RCAR_GP_PIN(2, 6), /* DU0_DR6 */
3518+
[ 4] = RCAR_GP_PIN(2, 5), /* DU0_DR5 */
3519+
[ 5] = RCAR_GP_PIN(2, 4), /* DU0_DR4 */
3520+
[ 6] = RCAR_GP_PIN(2, 3), /* DU0_DR3 */
3521+
[ 7] = RCAR_GP_PIN(2, 2), /* DU0_DR2 */
3522+
[ 8] = RCAR_GP_PIN(2, 1), /* DU0_DR1 */
3523+
[ 9] = RCAR_GP_PIN(2, 0), /* DU0_DR0 */
3524+
[10] = RCAR_GP_PIN(1, 22), /* EX_WAIT0 */
3525+
[11] = RCAR_GP_PIN(1, 21), /* QSPI0_SSL */
3526+
[12] = RCAR_GP_PIN(1, 20), /* QSPI0_IO3 */
3527+
[13] = RCAR_GP_PIN(1, 19), /* QSPI0_IO2 */
3528+
[14] = RCAR_GP_PIN(1, 18), /* QSPI0_MISO/QSPI0_IO1 */
3529+
[15] = RCAR_GP_PIN(1, 17), /* QSPI0_MOSI/QSPI0_IO0 */
3530+
[16] = RCAR_GP_PIN(1, 16), /* QSPI0_SPCLK */
3531+
[17] = RCAR_GP_PIN(1, 15), /* D15 */
3532+
[18] = RCAR_GP_PIN(1, 14), /* D14 */
3533+
[19] = RCAR_GP_PIN(1, 13), /* D13 */
3534+
[20] = RCAR_GP_PIN(1, 12), /* D12 */
3535+
[21] = RCAR_GP_PIN(1, 11), /* D11 */
3536+
[22] = RCAR_GP_PIN(1, 10), /* D10 */
3537+
[23] = RCAR_GP_PIN(1, 9), /* D9 */
3538+
[24] = RCAR_GP_PIN(1, 8), /* D8 */
3539+
[25] = RCAR_GP_PIN(1, 7), /* D7 */
3540+
[26] = RCAR_GP_PIN(1, 6), /* D6 */
3541+
[27] = RCAR_GP_PIN(1, 5), /* D5 */
3542+
[28] = RCAR_GP_PIN(1, 4), /* D4 */
3543+
[29] = RCAR_GP_PIN(1, 3), /* D3 */
3544+
[30] = RCAR_GP_PIN(1, 2), /* D2 */
3545+
[31] = RCAR_GP_PIN(1, 1), /* D1 */
3546+
} },
3547+
{ PINMUX_BIAS_REG("PUPR2", 0xe6060108, "N/A", 0) {
3548+
[ 0] = RCAR_GP_PIN(3, 9), /* VI1_CLKENB */
3549+
[ 1] = RCAR_GP_PIN(3, 8), /* VI1_DATA7 */
3550+
[ 2] = RCAR_GP_PIN(3, 7), /* VI1_DATA6 */
3551+
[ 3] = RCAR_GP_PIN(3, 6), /* VI1_DATA5 */
3552+
[ 4] = RCAR_GP_PIN(3, 5), /* VI1_DATA4 */
3553+
[ 5] = RCAR_GP_PIN(3, 4), /* VI1_DATA3 */
3554+
[ 6] = RCAR_GP_PIN(3, 3), /* VI1_DATA2 */
3555+
[ 7] = RCAR_GP_PIN(3, 2), /* VI1_DATA1 */
3556+
[ 8] = RCAR_GP_PIN(3, 1), /* VI1_DATA0 */
3557+
[ 9] = RCAR_GP_PIN(3, 0), /* VI1_CLK */
3558+
[10] = RCAR_GP_PIN(2, 31), /* DU0_CDE */
3559+
[11] = RCAR_GP_PIN(2, 30), /* DU0_DISP */
3560+
[12] = RCAR_GP_PIN(2, 29), /* DU0_EXODDF/DU0_ODDF_DISP_CDE */
3561+
[13] = RCAR_GP_PIN(2, 28), /* DU0_EXVSYNC/DU0_VSYNC */
3562+
[14] = RCAR_GP_PIN(2, 27), /* DU0_EXHSYNC/DU0_HSYNC */
3563+
[15] = RCAR_GP_PIN(2, 26), /* DU0_DOTCLKOUT1 */
3564+
[16] = RCAR_GP_PIN(2, 25), /* DU0_DOTCLKOUT0 */
3565+
[17] = RCAR_GP_PIN(2, 24), /* DU0_DOTCLKIN */
3566+
[18] = RCAR_GP_PIN(2, 23), /* DU0_DB7 */
3567+
[19] = RCAR_GP_PIN(2, 22), /* DU0_DB6 */
3568+
[20] = RCAR_GP_PIN(2, 21), /* DU0_DB5 */
3569+
[21] = RCAR_GP_PIN(2, 20), /* DU0_DB4 */
3570+
[22] = RCAR_GP_PIN(2, 19), /* DU0_DB3 */
3571+
[23] = RCAR_GP_PIN(2, 18), /* DU0_DB2 */
3572+
[24] = RCAR_GP_PIN(2, 17), /* DU0_DB1 */
3573+
[25] = RCAR_GP_PIN(2, 16), /* DU0_DB0 */
3574+
[26] = RCAR_GP_PIN(2, 15), /* DU0_DG7 */
3575+
[27] = RCAR_GP_PIN(2, 14), /* DU0_DG6 */
3576+
[28] = RCAR_GP_PIN(2, 13), /* DU0_DG5 */
3577+
[29] = RCAR_GP_PIN(2, 12), /* DU0_DG4 */
3578+
[30] = RCAR_GP_PIN(2, 11), /* DU0_DG3 */
3579+
[31] = RCAR_GP_PIN(2, 10), /* DU0_DG2 */
3580+
} },
3581+
{ PINMUX_BIAS_REG("PUPR3", 0xe606010c, "N/A", 0) {
3582+
[ 0] = RCAR_GP_PIN(4, 21), /* SD2_WP */
3583+
[ 1] = RCAR_GP_PIN(4, 20), /* SD2_CD */
3584+
[ 2] = RCAR_GP_PIN(4, 19), /* SD2_DAT3 */
3585+
[ 3] = RCAR_GP_PIN(4, 18), /* SD2_DAT2 */
3586+
[ 4] = RCAR_GP_PIN(4, 17), /* SD2_DAT1 */
3587+
[ 5] = RCAR_GP_PIN(4, 16), /* SD2_DAT0 */
3588+
[ 6] = RCAR_GP_PIN(4, 15), /* SD2_CMD */
3589+
[ 7] = RCAR_GP_PIN(4, 14), /* SD2_CLK */
3590+
[ 8] = RCAR_GP_PIN(4, 13), /* HRTS1#_A */
3591+
[ 9] = RCAR_GP_PIN(4, 12), /* HCTS1#_A */
3592+
[10] = RCAR_GP_PIN(4, 11), /* HTX1_A */
3593+
[11] = RCAR_GP_PIN(4, 10), /* HRX1_A */
3594+
[12] = RCAR_GP_PIN(4, 9), /* MSIOF0_SS2_A */
3595+
[13] = RCAR_GP_PIN(4, 8), /* MSIOF0_SS1_A */
3596+
[14] = RCAR_GP_PIN(4, 7), /* MSIOF0_SYNC_A */
3597+
[15] = RCAR_GP_PIN(4, 6), /* MSIOF0_SCK_A */
3598+
[16] = RCAR_GP_PIN(4, 5), /* MSIOF0_TXD_A */
3599+
[17] = RCAR_GP_PIN(4, 4), /* MSIOF0_RXD_A */
3600+
[18] = RCAR_GP_PIN(4, 3), /* SDA1_A */
3601+
[19] = RCAR_GP_PIN(4, 2), /* SCL1_A */
3602+
[20] = RCAR_GP_PIN(4, 1), /* SDA0_A */
3603+
[21] = RCAR_GP_PIN(4, 0), /* SCL0_A */
3604+
[22] = RCAR_GP_PIN(3, 29), /* AVB_TXD5 */
3605+
[23] = RCAR_GP_PIN(3, 28), /* AVB_TXD4 */
3606+
[24] = RCAR_GP_PIN(3, 27), /* AVB_TXD3 */
3607+
[25] = RCAR_GP_PIN(3, 16), /* VI1_DATA11 */
3608+
[26] = RCAR_GP_PIN(3, 15), /* VI1_DATA10 */
3609+
[27] = RCAR_GP_PIN(3, 14), /* VI1_DATA9 */
3610+
[28] = RCAR_GP_PIN(3, 13), /* VI1_DATA8 */
3611+
[29] = RCAR_GP_PIN(3, 12), /* VI1_VSYNC# */
3612+
[30] = RCAR_GP_PIN(3, 11), /* VI1_HSYNC# */
3613+
[31] = RCAR_GP_PIN(3, 10), /* VI1_FIELD */
3614+
} },
3615+
{ PINMUX_BIAS_REG("PUPR4", 0xe6060110, "N/A", 0) {
3616+
[ 0] = RCAR_GP_PIN(5, 27), /* SSI_SDATA9_A */
3617+
[ 1] = RCAR_GP_PIN(5, 26), /* SSI_WS9_A */
3618+
[ 2] = RCAR_GP_PIN(5, 25), /* SSI_SCK9_A */
3619+
[ 3] = RCAR_GP_PIN(5, 24), /* SSI_SDATA2_A */
3620+
[ 4] = RCAR_GP_PIN(5, 23), /* SSI_WS2_A */
3621+
[ 5] = RCAR_GP_PIN(5, 22), /* SSI_SCK2_A */
3622+
[ 6] = RCAR_GP_PIN(5, 21), /* SSI_SDATA1_A */
3623+
[ 7] = RCAR_GP_PIN(5, 20), /* SSI_WS1_A */
3624+
[ 8] = RCAR_GP_PIN(5, 19), /* SSI_SDATA8_A */
3625+
[ 9] = RCAR_GP_PIN(5, 18), /* SSI_SCK1_A */
3626+
[10] = RCAR_GP_PIN(5, 17), /* SSI_SDATA4_A */
3627+
[11] = RCAR_GP_PIN(5, 16), /* SSI_WS4_A */
3628+
[12] = RCAR_GP_PIN(5, 15), /* SSI_SCK4_A */
3629+
[13] = RCAR_GP_PIN(5, 14), /* SSI_SDATA3 */
3630+
[14] = RCAR_GP_PIN(5, 13), /* SSI_WS34 */
3631+
[15] = RCAR_GP_PIN(5, 12), /* SSI_SCK34 */
3632+
[16] = RCAR_GP_PIN(5, 11), /* SSI_SDATA0_A */
3633+
[17] = RCAR_GP_PIN(5, 10), /* SSI_WS0129_A */
3634+
[18] = RCAR_GP_PIN(5, 9), /* SSI_SCK0129_A */
3635+
[19] = RCAR_GP_PIN(5, 8), /* SSI_SDATA7_A */
3636+
[20] = RCAR_GP_PIN(5, 7), /* SSI_WS78_A */
3637+
[21] = RCAR_GP_PIN(5, 6), /* SSI_SCK78_A */
3638+
[22] = RCAR_GP_PIN(5, 5), /* SSI_SDATA6_A */
3639+
[23] = RCAR_GP_PIN(5, 4), /* SSI_WS6_A */
3640+
[24] = RCAR_GP_PIN(5, 3), /* SSI_SCK6_A */
3641+
[25] = RCAR_GP_PIN(5, 2), /* SSI_SDATA5_A */
3642+
[26] = RCAR_GP_PIN(5, 1), /* SSI_WS5_A */
3643+
[27] = RCAR_GP_PIN(5, 0), /* SSI_SCK5_A */
3644+
[28] = RCAR_GP_PIN(4, 25), /* SDA2_A */
3645+
[29] = RCAR_GP_PIN(4, 24), /* SCL2_A */
3646+
[30] = RCAR_GP_PIN(4, 23), /* TX3_A */
3647+
[31] = RCAR_GP_PIN(4, 22), /* RX3_A */
3648+
} },
3649+
{ PINMUX_BIAS_REG("PUPR5", 0xe6060114, "N/A", 0) {
3650+
[ 0] = SH_PFC_PIN_NONE,
3651+
[ 1] = SH_PFC_PIN_NONE,
3652+
[ 2] = SH_PFC_PIN_NONE,
3653+
[ 3] = SH_PFC_PIN_NONE,
3654+
[ 4] = SH_PFC_PIN_NONE,
3655+
[ 5] = SH_PFC_PIN_NONE,
3656+
[ 6] = SH_PFC_PIN_NONE,
3657+
[ 7] = SH_PFC_PIN_NONE,
3658+
[ 8] = SH_PFC_PIN_NONE,
3659+
[ 9] = SH_PFC_PIN_NONE,
3660+
[10] = SH_PFC_PIN_NONE,
3661+
[11] = SH_PFC_PIN_NONE,
3662+
[12] = SH_PFC_PIN_NONE,
3663+
[13] = SH_PFC_PIN_NONE,
3664+
[14] = SH_PFC_PIN_NONE,
3665+
[15] = SH_PFC_PIN_NONE,
3666+
[16] = SH_PFC_PIN_NONE,
3667+
[17] = SH_PFC_PIN_NONE,
3668+
[18] = SH_PFC_PIN_NONE,
3669+
[19] = SH_PFC_PIN_NONE,
3670+
[20] = SH_PFC_PIN_NONE,
3671+
[21] = SH_PFC_PIN_NONE,
3672+
[22] = SH_PFC_PIN_NONE,
3673+
[23] = SH_PFC_PIN_NONE,
3674+
[24] = SH_PFC_PIN_NONE,
3675+
[25] = SH_PFC_PIN_NONE,
3676+
[26] = SH_PFC_PIN_NONE,
3677+
[27] = SH_PFC_PIN_NONE,
3678+
[28] = RCAR_GP_PIN(5, 31), /* AUDIO_CLKOUT_A */
3679+
[29] = RCAR_GP_PIN(5, 30), /* AUDIO_CLKC_A */
3680+
[30] = RCAR_GP_PIN(5, 29), /* AUDIO_CLKB_A */
3681+
[31] = RCAR_GP_PIN(5, 28), /* AUDIO_CLKA_A */
3682+
} },
3683+
{ /* sentinel */ }
3684+
};
3685+
34233686
static const struct sh_pfc_soc_operations r8a77470_pinmux_ops = {
34243687
.pin_to_pocctrl = r8a77470_pin_to_pocctrl,
3688+
.get_bias = rcar_pinmux_get_bias,
3689+
.set_bias = rcar_pinmux_set_bias,
34253690
};
34263691

34273692
#ifdef CONFIG_PINCTRL_PFC_R8A77470
@@ -3440,6 +3705,7 @@ const struct sh_pfc_soc_info r8a77470_pinmux_info = {
34403705
.nr_functions = ARRAY_SIZE(pinmux_functions),
34413706

34423707
.cfg_regs = pinmux_config_regs,
3708+
.bias_regs = pinmux_bias_regs,
34433709

34443710
.pinmux_data = pinmux_data,
34453711
.pinmux_data_size = ARRAY_SIZE(pinmux_data),

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