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Wesley Chalmersalexdeucher
Wesley Chalmers
authored and
alexdeucher
committed
drm/amd/display: Add interface for ADD & DROP PIXEL Registers
[WHY] HW has handed down a new sequence that requires access to these registers. v2: squash in DCN3.1 fixes (Alex) Signed-off-by: Wesley Chalmers <[email protected]> Reviewed-by: Dmytro Laktyushkin <[email protected]> Acked-by: Stylon Wang <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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8 files changed

+101
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‎drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c

Lines changed: 26 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -105,6 +105,30 @@ void dccg2_set_fifo_errdet_ovr_en(struct dccg *dccg,
105105
DCCG_FIFO_ERRDET_OVR_EN, en ? 1 : 0);
106106
}
107107

108+
void dccg2_otg_add_pixel(struct dccg *dccg,
109+
uint32_t otg_inst)
110+
{
111+
struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
112+
113+
REG_UPDATE_2(OTG_PIXEL_RATE_CNTL[otg_inst],
114+
OTG_ADD_PIXEL[otg_inst], 0,
115+
OTG_DROP_PIXEL[otg_inst], 0);
116+
REG_UPDATE(OTG_PIXEL_RATE_CNTL[otg_inst],
117+
OTG_ADD_PIXEL[otg_inst], 1);
118+
}
119+
120+
void dccg2_otg_drop_pixel(struct dccg *dccg,
121+
uint32_t otg_inst)
122+
{
123+
struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
124+
125+
REG_UPDATE_2(OTG_PIXEL_RATE_CNTL[otg_inst],
126+
OTG_ADD_PIXEL[otg_inst], 0,
127+
OTG_DROP_PIXEL[otg_inst], 0);
128+
REG_UPDATE(OTG_PIXEL_RATE_CNTL[otg_inst],
129+
OTG_DROP_PIXEL[otg_inst], 1);
130+
}
131+
108132
void dccg2_init(struct dccg *dccg)
109133
{
110134
}
@@ -113,6 +137,8 @@ static const struct dccg_funcs dccg2_funcs = {
113137
.update_dpp_dto = dccg2_update_dpp_dto,
114138
.get_dccg_ref_freq = dccg2_get_dccg_ref_freq,
115139
.set_fifo_errdet_ovr_en = dccg2_set_fifo_errdet_ovr_en,
140+
.otg_add_pixel = dccg2_otg_add_pixel,
141+
.otg_drop_pixel = dccg2_otg_drop_pixel,
116142
.dccg_init = dccg2_init
117143
};
118144

‎drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h

Lines changed: 47 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -35,19 +35,28 @@
3535
DCCG_SRII(DTO_PARAM, DPPCLK, 2),\
3636
DCCG_SRII(DTO_PARAM, DPPCLK, 3),\
3737
SR(REFCLK_CNTL),\
38+
DCCG_SRII(PIXEL_RATE_CNTL, OTG, 0),\
39+
DCCG_SRII(PIXEL_RATE_CNTL, OTG, 1),\
3840
SR(DISPCLK_FREQ_CHANGE_CNTL)
3941

4042
#define DCCG_REG_LIST_DCN2() \
4143
DCCG_COMMON_REG_LIST_DCN_BASE(),\
4244
DCCG_SRII(DTO_PARAM, DPPCLK, 4),\
43-
DCCG_SRII(DTO_PARAM, DPPCLK, 5)
45+
DCCG_SRII(DTO_PARAM, DPPCLK, 5),\
46+
DCCG_SRII(PIXEL_RATE_CNTL, OTG, 2),\
47+
DCCG_SRII(PIXEL_RATE_CNTL, OTG, 3),\
48+
DCCG_SRII(PIXEL_RATE_CNTL, OTG, 4),\
49+
DCCG_SRII(PIXEL_RATE_CNTL, OTG, 5)
4450

4551
#define DCCG_SF(reg_name, field_name, post_fix)\
4652
.field_name = reg_name ## __ ## field_name ## post_fix
4753

4854
#define DCCG_SFI(reg_name, field_name, field_prefix, inst, post_fix)\
4955
.field_prefix ## _ ## field_name[inst] = reg_name ## __ ## field_prefix ## inst ## _ ## field_name ## post_fix
5056

57+
#define DCCG_SFII(block, reg_name, field_prefix, field_name, inst, post_fix)\
58+
.field_prefix ## _ ## field_name[inst] = block ## inst ## _ ## reg_name ## __ ## field_prefix ## inst ## _ ## field_name ## post_fix
59+
5160
#define DCCG_COMMON_MASK_SH_LIST_DCN_COMMON_BASE(mask_sh) \
5261
DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 0, mask_sh),\
5362
DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 0, mask_sh),\
@@ -68,15 +77,41 @@
6877
DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DCCG_FIFO_ERRDET_RESET, mask_sh),\
6978
DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DCCG_FIFO_ERRDET_STATE, mask_sh),\
7079
DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DCCG_FIFO_ERRDET_OVR_EN, mask_sh),\
71-
DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_CHG_FWD_CORR_DISABLE, mask_sh)
80+
DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_CHG_FWD_CORR_DISABLE, mask_sh),\
81+
DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 0, mask_sh),\
82+
DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 1, mask_sh),\
83+
DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 0, mask_sh),\
84+
DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 1, mask_sh)
85+
86+
7287

7388

7489
#define DCCG_MASK_SH_LIST_DCN2(mask_sh) \
7590
DCCG_COMMON_MASK_SH_LIST_DCN_COMMON_BASE(mask_sh),\
7691
DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 4, mask_sh),\
7792
DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 4, mask_sh),\
7893
DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 5, mask_sh),\
79-
DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 5, mask_sh)
94+
DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 5, mask_sh),\
95+
DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 2, mask_sh),\
96+
DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 3, mask_sh),\
97+
DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 4, mask_sh),\
98+
DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 5, mask_sh),\
99+
DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 2, mask_sh),\
100+
DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 3, mask_sh),\
101+
DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 4, mask_sh),\
102+
DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 5, mask_sh)
103+
104+
#define DCCG_MASK_SH_LIST_DCN2_1(mask_sh) \
105+
DCCG_COMMON_MASK_SH_LIST_DCN_COMMON_BASE(mask_sh),\
106+
DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 4, mask_sh),\
107+
DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 4, mask_sh),\
108+
DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 5, mask_sh),\
109+
DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 5, mask_sh),\
110+
DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 2, mask_sh),\
111+
DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 3, mask_sh),\
112+
DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 2, mask_sh),\
113+
DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 3, mask_sh)
114+
80115

81116
#define DCCG_REG_FIELD_LIST(type) \
82117
type DPPCLK0_DTO_PHASE;\
@@ -93,7 +128,9 @@
93128
type DCCG_FIFO_ERRDET_STATE;\
94129
type DCCG_FIFO_ERRDET_OVR_EN;\
95130
type DISPCLK_CHG_FWD_CORR_DISABLE;\
96-
type DISPCLK_FREQ_CHANGE_CNTL;
131+
type DISPCLK_FREQ_CHANGE_CNTL;\
132+
type OTG_ADD_PIXEL[MAX_PIPES];\
133+
type OTG_DROP_PIXEL[MAX_PIPES];
97134

98135
#define DCCG3_REG_FIELD_LIST(type) \
99136
type PHYASYMCLK_FORCE_EN;\
@@ -157,14 +194,14 @@ struct dccg_registers {
157194
uint32_t DPPCLK_DTO_PARAM[6];
158195
uint32_t REFCLK_CNTL;
159196
uint32_t DISPCLK_FREQ_CHANGE_CNTL;
197+
uint32_t OTG_PIXEL_RATE_CNTL[MAX_PIPES];
160198
uint32_t HDMICHARCLK_CLOCK_CNTL[6];
161199
uint32_t PHYASYMCLK_CLOCK_CNTL;
162200
uint32_t PHYBSYMCLK_CLOCK_CNTL;
163201
uint32_t PHYCSYMCLK_CLOCK_CNTL;
164202
#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
165203
uint32_t PHYDSYMCLK_CLOCK_CNTL;
166204
uint32_t PHYESYMCLK_CLOCK_CNTL;
167-
uint32_t OTG_PIXEL_RATE_CNTL[MAX_PIPES];
168205
uint32_t DTBCLK_DTO_MODULO[MAX_PIPES];
169206
uint32_t DTBCLK_DTO_PHASE[MAX_PIPES];
170207
uint32_t DCCG_AUDIO_DTBCLK_DTO_MODULO;
@@ -193,6 +230,11 @@ void dccg2_get_dccg_ref_freq(struct dccg *dccg,
193230

194231
void dccg2_set_fifo_errdet_ovr_en(struct dccg *dccg,
195232
bool en);
233+
void dccg2_otg_add_pixel(struct dccg *dccg,
234+
uint32_t otg_inst);
235+
void dccg2_otg_drop_pixel(struct dccg *dccg,
236+
uint32_t otg_inst);
237+
196238

197239
void dccg2_init(struct dccg *dccg);
198240

‎drivers/gpu/drm/amd/display/dc/dcn21/dcn21_dccg.c

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -101,6 +101,8 @@ static const struct dccg_funcs dccg21_funcs = {
101101
.update_dpp_dto = dccg21_update_dpp_dto,
102102
.get_dccg_ref_freq = dccg2_get_dccg_ref_freq,
103103
.set_fifo_errdet_ovr_en = dccg2_set_fifo_errdet_ovr_en,
104+
.otg_add_pixel = dccg2_otg_add_pixel,
105+
.otg_drop_pixel = dccg2_otg_drop_pixel,
104106
.dccg_init = dccg2_init
105107
};
106108

‎drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -448,11 +448,11 @@ static const struct dccg_registers dccg_regs = {
448448
};
449449

450450
static const struct dccg_shift dccg_shift = {
451-
DCCG_MASK_SH_LIST_DCN2(__SHIFT)
451+
DCCG_MASK_SH_LIST_DCN2_1(__SHIFT)
452452
};
453453

454454
static const struct dccg_mask dccg_mask = {
455-
DCCG_MASK_SH_LIST_DCN2(_MASK)
455+
DCCG_MASK_SH_LIST_DCN2_1(_MASK)
456456
};
457457

458458
#define opp_regs(id)\

‎drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dccg.c

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -47,6 +47,8 @@ static const struct dccg_funcs dccg3_funcs = {
4747
.update_dpp_dto = dccg2_update_dpp_dto,
4848
.get_dccg_ref_freq = dccg2_get_dccg_ref_freq,
4949
.set_fifo_errdet_ovr_en = dccg2_set_fifo_errdet_ovr_en,
50+
.otg_add_pixel = dccg2_otg_add_pixel,
51+
.otg_drop_pixel = dccg2_otg_drop_pixel,
5052
.dccg_init = dccg2_init
5153
};
5254

‎drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dccg.h

Lines changed: 16 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -38,18 +38,33 @@
3838

3939
#define DCCG_REG_LIST_DCN30() \
4040
DCCG_REG_LIST_DCN2(),\
41+
DCCG_SRII(PIXEL_RATE_CNTL, OTG, 2),\
42+
DCCG_SRII(PIXEL_RATE_CNTL, OTG, 3),\
43+
DCCG_SRII(PIXEL_RATE_CNTL, OTG, 4),\
44+
DCCG_SRII(PIXEL_RATE_CNTL, OTG, 5),\
4145
SR(PHYASYMCLK_CLOCK_CNTL),\
4246
SR(PHYBSYMCLK_CLOCK_CNTL),\
4347
SR(PHYCSYMCLK_CLOCK_CNTL)
4448

49+
#define DCCG_MASK_SH_LIST_DCN3AG(mask_sh) \
50+
DCCG_MASK_SH_LIST_DCN2_1(mask_sh),\
51+
DCCG_SF(HDMICHARCLK0_CLOCK_CNTL, HDMICHARCLK0_EN, mask_sh),\
52+
DCCG_SF(HDMICHARCLK0_CLOCK_CNTL, HDMICHARCLK0_SRC_SEL, mask_sh),\
53+
DCCG_SF(PHYASYMCLK_CLOCK_CNTL, PHYASYMCLK_FORCE_EN, mask_sh),\
54+
DCCG_SF(PHYASYMCLK_CLOCK_CNTL, PHYASYMCLK_FORCE_SRC_SEL, mask_sh),\
55+
DCCG_SF(PHYBSYMCLK_CLOCK_CNTL, PHYBSYMCLK_FORCE_EN, mask_sh),\
56+
DCCG_SF(PHYBSYMCLK_CLOCK_CNTL, PHYBSYMCLK_FORCE_SRC_SEL, mask_sh),\
57+
DCCG_SF(PHYCSYMCLK_CLOCK_CNTL, PHYCSYMCLK_FORCE_EN, mask_sh),\
58+
DCCG_SF(PHYCSYMCLK_CLOCK_CNTL, PHYCSYMCLK_FORCE_SRC_SEL, mask_sh)
59+
4560
#define DCCG_MASK_SH_LIST_DCN3(mask_sh) \
4661
DCCG_MASK_SH_LIST_DCN2(mask_sh),\
4762
DCCG_SF(PHYASYMCLK_CLOCK_CNTL, PHYASYMCLK_FORCE_EN, mask_sh),\
4863
DCCG_SF(PHYASYMCLK_CLOCK_CNTL, PHYASYMCLK_FORCE_SRC_SEL, mask_sh),\
4964
DCCG_SF(PHYBSYMCLK_CLOCK_CNTL, PHYBSYMCLK_FORCE_EN, mask_sh),\
5065
DCCG_SF(PHYBSYMCLK_CLOCK_CNTL, PHYBSYMCLK_FORCE_SRC_SEL, mask_sh),\
5166
DCCG_SF(PHYCSYMCLK_CLOCK_CNTL, PHYCSYMCLK_FORCE_EN, mask_sh),\
52-
DCCG_SF(PHYCSYMCLK_CLOCK_CNTL, PHYCSYMCLK_FORCE_SRC_SEL, mask_sh)
67+
DCCG_SF(PHYCSYMCLK_CLOCK_CNTL, PHYCSYMCLK_FORCE_SRC_SEL, mask_sh),\
5368

5469
struct dccg *dccg3_create(
5570
struct dc_context *ctx,

‎drivers/gpu/drm/amd/display/dc/dcn301/dcn301_dccg.c

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -46,6 +46,8 @@ static const struct dccg_funcs dccg301_funcs = {
4646
.update_dpp_dto = dccg2_update_dpp_dto,
4747
.get_dccg_ref_freq = dccg2_get_dccg_ref_freq,
4848
.set_fifo_errdet_ovr_en = dccg2_set_fifo_errdet_ovr_en,
49+
.otg_add_pixel = dccg2_otg_add_pixel,
50+
.otg_drop_pixel = dccg2_otg_drop_pixel,
4951
.dccg_init = dccg2_init
5052
};
5153

‎drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -78,6 +78,10 @@ struct dccg_funcs {
7878
unsigned int *dccg_ref_freq_inKhz);
7979
void (*set_fifo_errdet_ovr_en)(struct dccg *dccg,
8080
bool en);
81+
void (*otg_add_pixel)(struct dccg *dccg,
82+
uint32_t otg_inst);
83+
void (*otg_drop_pixel)(struct dccg *dccg,
84+
uint32_t otg_inst);
8185
void (*dccg_init)(struct dccg *dccg);
8286
#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
8387

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