Skip to content

Commit 4537f6f

Browse files
Zhen Leiwilldeacon
authored andcommitted
iommu/arm-smmu-v3: Add and use static helper function arm_smmu_cmdq_issue_cmd_with_sync()
The obvious key to the performance optimization of commit 587e6c1 ("iommu/arm-smmu-v3: Reduce contention during command-queue insertion") is to allow multiple cores to insert commands in parallel after a brief mutex contention. Obviously, inserting as many commands at a time as possible can reduce the number of times the mutex contention participates, thereby improving the overall performance. At least it reduces the number of calls to function arm_smmu_cmdq_issue_cmdlist(). Therefore, function arm_smmu_cmdq_issue_cmd_with_sync() is added to insert the 'cmd+sync' commands at a time. Signed-off-by: Zhen Lei <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Will Deacon <[email protected]>
1 parent eff1947 commit 4537f6f

File tree

1 file changed

+19
-16
lines changed

1 file changed

+19
-16
lines changed

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c

Lines changed: 19 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -845,8 +845,9 @@ static int arm_smmu_cmdq_issue_cmdlist(struct arm_smmu_device *smmu,
845845
return ret;
846846
}
847847

848-
static int arm_smmu_cmdq_issue_cmd(struct arm_smmu_device *smmu,
849-
struct arm_smmu_cmdq_ent *ent)
848+
static int __arm_smmu_cmdq_issue_cmd(struct arm_smmu_device *smmu,
849+
struct arm_smmu_cmdq_ent *ent,
850+
bool sync)
850851
{
851852
u64 cmd[CMDQ_ENT_DWORDS];
852853

@@ -856,12 +857,19 @@ static int arm_smmu_cmdq_issue_cmd(struct arm_smmu_device *smmu,
856857
return -EINVAL;
857858
}
858859

859-
return arm_smmu_cmdq_issue_cmdlist(smmu, cmd, 1, false);
860+
return arm_smmu_cmdq_issue_cmdlist(smmu, cmd, 1, sync);
860861
}
861862

862-
static int arm_smmu_cmdq_issue_sync(struct arm_smmu_device *smmu)
863+
static int arm_smmu_cmdq_issue_cmd(struct arm_smmu_device *smmu,
864+
struct arm_smmu_cmdq_ent *ent)
863865
{
864-
return arm_smmu_cmdq_issue_cmdlist(smmu, NULL, 0, true);
866+
return __arm_smmu_cmdq_issue_cmd(smmu, ent, false);
867+
}
868+
869+
static int arm_smmu_cmdq_issue_cmd_with_sync(struct arm_smmu_device *smmu,
870+
struct arm_smmu_cmdq_ent *ent)
871+
{
872+
return __arm_smmu_cmdq_issue_cmd(smmu, ent, true);
865873
}
866874

867875
static void arm_smmu_cmdq_batch_add(struct arm_smmu_device *smmu,
@@ -929,8 +937,7 @@ void arm_smmu_tlb_inv_asid(struct arm_smmu_device *smmu, u16 asid)
929937
.tlbi.asid = asid,
930938
};
931939

932-
arm_smmu_cmdq_issue_cmd(smmu, &cmd);
933-
arm_smmu_cmdq_issue_sync(smmu);
940+
arm_smmu_cmdq_issue_cmd_with_sync(smmu, &cmd);
934941
}
935942

936943
static void arm_smmu_sync_cd(struct arm_smmu_domain *smmu_domain,
@@ -1211,8 +1218,7 @@ static void arm_smmu_sync_ste_for_sid(struct arm_smmu_device *smmu, u32 sid)
12111218
},
12121219
};
12131220

1214-
arm_smmu_cmdq_issue_cmd(smmu, &cmd);
1215-
arm_smmu_cmdq_issue_sync(smmu);
1221+
arm_smmu_cmdq_issue_cmd_with_sync(smmu, &cmd);
12161222
}
12171223

12181224
static void arm_smmu_write_strtab_ent(struct arm_smmu_master *master, u32 sid,
@@ -1824,8 +1830,7 @@ static void arm_smmu_tlb_inv_context(void *cookie)
18241830
} else {
18251831
cmd.opcode = CMDQ_OP_TLBI_S12_VMALL;
18261832
cmd.tlbi.vmid = smmu_domain->s2_cfg.vmid;
1827-
arm_smmu_cmdq_issue_cmd(smmu, &cmd);
1828-
arm_smmu_cmdq_issue_sync(smmu);
1833+
arm_smmu_cmdq_issue_cmd_with_sync(smmu, &cmd);
18291834
}
18301835
arm_smmu_atc_inv_domain(smmu_domain, 0, 0, 0);
18311836
}
@@ -3339,18 +3344,16 @@ static int arm_smmu_device_reset(struct arm_smmu_device *smmu, bool bypass)
33393344

33403345
/* Invalidate any cached configuration */
33413346
cmd.opcode = CMDQ_OP_CFGI_ALL;
3342-
arm_smmu_cmdq_issue_cmd(smmu, &cmd);
3343-
arm_smmu_cmdq_issue_sync(smmu);
3347+
arm_smmu_cmdq_issue_cmd_with_sync(smmu, &cmd);
33443348

33453349
/* Invalidate any stale TLB entries */
33463350
if (smmu->features & ARM_SMMU_FEAT_HYP) {
33473351
cmd.opcode = CMDQ_OP_TLBI_EL2_ALL;
3348-
arm_smmu_cmdq_issue_cmd(smmu, &cmd);
3352+
arm_smmu_cmdq_issue_cmd_with_sync(smmu, &cmd);
33493353
}
33503354

33513355
cmd.opcode = CMDQ_OP_TLBI_NSNH_ALL;
3352-
arm_smmu_cmdq_issue_cmd(smmu, &cmd);
3353-
arm_smmu_cmdq_issue_sync(smmu);
3356+
arm_smmu_cmdq_issue_cmd_with_sync(smmu, &cmd);
33543357

33553358
/* Event queue */
33563359
writeq_relaxed(smmu->evtq.q.q_base, smmu->base + ARM_SMMU_EVTQ_BASE);

0 commit comments

Comments
 (0)