Skip to content

Commit 4990d8c

Browse files
bebarinobebarino
committed
Merge branches 'clk-qcom', 'clk-socfpga', 'clk-mediatek', 'clk-lmk' and 'clk-x86' into clk-next
 - Support video, gpu, display clks on qcom sc7280 SoCs - GCC clks on qcom MSM8953, SM4250/6115, and SM6350 SoCs - Multimedia clks (MMCC) on qcom MSM8994/MSM8992 - Migrate to clk_parent_data in gcc-sdm660 - RPMh clks on qcom SM6350 SoCs - Support for Mediatek MT8192 SoCs * clk-qcom: (38 commits) clk: qcom: Add SM6350 GCC driver dt-bindings: clock: Add SM6350 GCC clock bindings clk: qcom: rpmh: Add support for RPMH clocks on SM6350 dt-bindings: clock: Add RPMHCC bindings for SM6350 clk: qcom: adjust selects for SM_VIDEOCC_8150 and SM_VIDEOCC_8250 clk: qcom: Add Global Clock controller (GCC) driver for SM6115 dt-bindings: clk: qcom: gcc-sm6115: Document SM6115 GCC clk: qcom: mmcc-msm8994: Add MSM8992 support clk: qcom: Add msm8994 MMCC driver dt-bindings: clock: Add support for MSM8992/4 MMCC clk: qcom: Add Global Clock Controller driver for MSM8953 dt-bindings: clock: add Qualcomm MSM8953 GCC driver bindings clk: qcom: gcc-sdm660: Replace usage of parent_names clk: qcom: gcc-sdm660: Move parent tables after PLLs clk: qcom: use devm_pm_runtime_enable and devm_pm_clk_create PM: runtime: add devm_pm_clk_create helper PM: runtime: add devm_pm_runtime_enable helper clk: qcom: a53-pll: Add MSM8939 a53pll support dt-bindings: clock: Update qcom,a53pll bindings for MSM8939 support clk: qcom: a53pll/mux: Use unique clock name ... * clk-socfpga: clk: socfpga: agilex: add the bypass register for s2f_usr0 clock clk: socfpga: agilex: fix up s2f_user0_clk representation clk: socfpga: agilex: fix the parents of the psi_ref_clk * clk-mediatek: (22 commits) clk: mediatek: make COMMON_CLK_MT8167* depend on COMMON_CLK_MT8167 clk: mediatek: Add MT8192 vencsys clock support clk: mediatek: Add MT8192 vdecsys clock support clk: mediatek: Add MT8192 scp adsp clock support clk: mediatek: Add MT8192 msdc clock support clk: mediatek: Add MT8192 mmsys clock support clk: mediatek: Add MT8192 mfgcfg clock support clk: mediatek: Add MT8192 mdpsys clock support clk: mediatek: Add MT8192 ipesys clock support clk: mediatek: Add MT8192 imp i2c wrapper clock support clk: mediatek: Add MT8192 imgsys clock support clk: mediatek: Add MT8192 camsys clock support clk: mediatek: Add MT8192 audio clock support clk: mediatek: Add MT8192 basic clocks support clk: mediatek: Add mtk_clk_simple_probe() to simplify clock providers clk: mediatek: Add configurable enable control to mtk_pll_data clk: mediatek: Fix asymmetrical PLL enable and disable control clk: mediatek: Get regmap without syscon compatible check clk: mediatek: Add dt-bindings of MT8192 clocks dt-bindings: ARM: Mediatek: Add audsys document binding for MT8192 ... * clk-lmk: clk: lmk04832: drop redundant fallthrough statements * clk-x86: clk: x86: Rename clk-lpt to more specific clk-lpss-atom
6 parents 2734d6c + 131abae + d17929e + d17e4e6 + 284c537 + cf0a956 commit 4990d8c

Some content is hidden

Large Commits have some content hidden by default. Use the searchbox below for content that may be hidden.

80 files changed

+19971
-447
lines changed

‎Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -13,6 +13,7 @@ Required Properties:
1313
- "mediatek,mt7623-audsys", "mediatek,mt2701-audsys", "syscon"
1414
- "mediatek,mt8167-audiosys", "syscon"
1515
- "mediatek,mt8183-audiosys", "syscon"
16+
- "mediatek,mt8192-audsys", "syscon"
1617
- "mediatek,mt8516-audsys", "syscon"
1718
- #clock-cells: Must be 1
1819

‎Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -16,6 +16,7 @@ Required Properties:
1616
- "mediatek,mt8167-mmsys", "syscon"
1717
- "mediatek,mt8173-mmsys", "syscon"
1818
- "mediatek,mt8183-mmsys", "syscon"
19+
- "mediatek,mt8192-mmsys", "syscon"
1920
- #clock-cells: Must be 1
2021

2122
For the clock control, the mmsys controller uses the common clk binding from

‎Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-clock.yaml

Lines changed: 199 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,199 @@
1+
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2+
%YAML 1.2
3+
---
4+
$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt8192-clock.yaml#"
5+
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
6+
7+
title: MediaTek Functional Clock Controller for MT8192
8+
9+
maintainers:
10+
- Chun-Jie Chen <[email protected]>
11+
12+
description:
13+
The Mediatek functional clock controller provides various clocks on MT8192.
14+
15+
properties:
16+
compatible:
17+
items:
18+
- enum:
19+
- mediatek,mt8192-scp_adsp
20+
- mediatek,mt8192-imp_iic_wrap_c
21+
- mediatek,mt8192-imp_iic_wrap_e
22+
- mediatek,mt8192-imp_iic_wrap_s
23+
- mediatek,mt8192-imp_iic_wrap_ws
24+
- mediatek,mt8192-imp_iic_wrap_w
25+
- mediatek,mt8192-imp_iic_wrap_n
26+
- mediatek,mt8192-msdc_top
27+
- mediatek,mt8192-msdc
28+
- mediatek,mt8192-mfgcfg
29+
- mediatek,mt8192-imgsys
30+
- mediatek,mt8192-imgsys2
31+
- mediatek,mt8192-vdecsys_soc
32+
- mediatek,mt8192-vdecsys
33+
- mediatek,mt8192-vencsys
34+
- mediatek,mt8192-camsys
35+
- mediatek,mt8192-camsys_rawa
36+
- mediatek,mt8192-camsys_rawb
37+
- mediatek,mt8192-camsys_rawc
38+
- mediatek,mt8192-ipesys
39+
- mediatek,mt8192-mdpsys
40+
41+
reg:
42+
maxItems: 1
43+
44+
'#clock-cells':
45+
const: 1
46+
47+
required:
48+
- compatible
49+
- reg
50+
51+
additionalProperties: false
52+
53+
examples:
54+
- |
55+
scp_adsp: clock-controller@10720000 {
56+
compatible = "mediatek,mt8192-scp_adsp";
57+
reg = <0x10720000 0x1000>;
58+
#clock-cells = <1>;
59+
};
60+
61+
- |
62+
imp_iic_wrap_c: clock-controller@11007000 {
63+
compatible = "mediatek,mt8192-imp_iic_wrap_c";
64+
reg = <0x11007000 0x1000>;
65+
#clock-cells = <1>;
66+
};
67+
68+
- |
69+
imp_iic_wrap_e: clock-controller@11cb1000 {
70+
compatible = "mediatek,mt8192-imp_iic_wrap_e";
71+
reg = <0x11cb1000 0x1000>;
72+
#clock-cells = <1>;
73+
};
74+
75+
- |
76+
imp_iic_wrap_s: clock-controller@11d03000 {
77+
compatible = "mediatek,mt8192-imp_iic_wrap_s";
78+
reg = <0x11d03000 0x1000>;
79+
#clock-cells = <1>;
80+
};
81+
82+
- |
83+
imp_iic_wrap_ws: clock-controller@11d23000 {
84+
compatible = "mediatek,mt8192-imp_iic_wrap_ws";
85+
reg = <0x11d23000 0x1000>;
86+
#clock-cells = <1>;
87+
};
88+
89+
- |
90+
imp_iic_wrap_w: clock-controller@11e01000 {
91+
compatible = "mediatek,mt8192-imp_iic_wrap_w";
92+
reg = <0x11e01000 0x1000>;
93+
#clock-cells = <1>;
94+
};
95+
96+
- |
97+
imp_iic_wrap_n: clock-controller@11f02000 {
98+
compatible = "mediatek,mt8192-imp_iic_wrap_n";
99+
reg = <0x11f02000 0x1000>;
100+
#clock-cells = <1>;
101+
};
102+
103+
- |
104+
msdc_top: clock-controller@11f10000 {
105+
compatible = "mediatek,mt8192-msdc_top";
106+
reg = <0x11f10000 0x1000>;
107+
#clock-cells = <1>;
108+
};
109+
110+
- |
111+
msdc: clock-controller@11f60000 {
112+
compatible = "mediatek,mt8192-msdc";
113+
reg = <0x11f60000 0x1000>;
114+
#clock-cells = <1>;
115+
};
116+
117+
- |
118+
mfgcfg: clock-controller@13fbf000 {
119+
compatible = "mediatek,mt8192-mfgcfg";
120+
reg = <0x13fbf000 0x1000>;
121+
#clock-cells = <1>;
122+
};
123+
124+
- |
125+
imgsys: clock-controller@15020000 {
126+
compatible = "mediatek,mt8192-imgsys";
127+
reg = <0x15020000 0x1000>;
128+
#clock-cells = <1>;
129+
};
130+
131+
- |
132+
imgsys2: clock-controller@15820000 {
133+
compatible = "mediatek,mt8192-imgsys2";
134+
reg = <0x15820000 0x1000>;
135+
#clock-cells = <1>;
136+
};
137+
138+
- |
139+
vdecsys_soc: clock-controller@1600f000 {
140+
compatible = "mediatek,mt8192-vdecsys_soc";
141+
reg = <0x1600f000 0x1000>;
142+
#clock-cells = <1>;
143+
};
144+
145+
- |
146+
vdecsys: clock-controller@1602f000 {
147+
compatible = "mediatek,mt8192-vdecsys";
148+
reg = <0x1602f000 0x1000>;
149+
#clock-cells = <1>;
150+
};
151+
152+
- |
153+
vencsys: clock-controller@17000000 {
154+
compatible = "mediatek,mt8192-vencsys";
155+
reg = <0x17000000 0x1000>;
156+
#clock-cells = <1>;
157+
};
158+
159+
- |
160+
camsys: clock-controller@1a000000 {
161+
compatible = "mediatek,mt8192-camsys";
162+
reg = <0x1a000000 0x1000>;
163+
#clock-cells = <1>;
164+
};
165+
166+
- |
167+
camsys_rawa: clock-controller@1a04f000 {
168+
compatible = "mediatek,mt8192-camsys_rawa";
169+
reg = <0x1a04f000 0x1000>;
170+
#clock-cells = <1>;
171+
};
172+
173+
- |
174+
camsys_rawb: clock-controller@1a06f000 {
175+
compatible = "mediatek,mt8192-camsys_rawb";
176+
reg = <0x1a06f000 0x1000>;
177+
#clock-cells = <1>;
178+
};
179+
180+
- |
181+
camsys_rawc: clock-controller@1a08f000 {
182+
compatible = "mediatek,mt8192-camsys_rawc";
183+
reg = <0x1a08f000 0x1000>;
184+
#clock-cells = <1>;
185+
};
186+
187+
- |
188+
ipesys: clock-controller@1b000000 {
189+
compatible = "mediatek,mt8192-ipesys";
190+
reg = <0x1b000000 0x1000>;
191+
#clock-cells = <1>;
192+
};
193+
194+
- |
195+
mdpsys: clock-controller@1f000000 {
196+
compatible = "mediatek,mt8192-mdpsys";
197+
reg = <0x1f000000 0x1000>;
198+
#clock-cells = <1>;
199+
};

‎Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-sys-clock.yaml

Lines changed: 65 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,65 @@
1+
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2+
%YAML 1.2
3+
---
4+
$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt8192-sys-clock.yaml#"
5+
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
6+
7+
title: MediaTek System Clock Controller for MT8192
8+
9+
maintainers:
10+
- Chun-Jie Chen <[email protected]>
11+
12+
description:
13+
The Mediatek system clock controller provides various clocks and system configuration
14+
like reset and bus protection on MT8192.
15+
16+
properties:
17+
compatible:
18+
items:
19+
- enum:
20+
- mediatek,mt8192-topckgen
21+
- mediatek,mt8192-infracfg
22+
- mediatek,mt8192-pericfg
23+
- mediatek,mt8192-apmixedsys
24+
- const: syscon
25+
26+
reg:
27+
maxItems: 1
28+
29+
'#clock-cells':
30+
const: 1
31+
32+
required:
33+
- compatible
34+
- reg
35+
36+
additionalProperties: false
37+
38+
examples:
39+
- |
40+
topckgen: syscon@10000000 {
41+
compatible = "mediatek,mt8192-topckgen", "syscon";
42+
reg = <0x10000000 0x1000>;
43+
#clock-cells = <1>;
44+
};
45+
46+
- |
47+
infracfg: syscon@10001000 {
48+
compatible = "mediatek,mt8192-infracfg", "syscon";
49+
reg = <0x10001000 0x1000>;
50+
#clock-cells = <1>;
51+
};
52+
53+
- |
54+
pericfg: syscon@10003000 {
55+
compatible = "mediatek,mt8192-pericfg", "syscon";
56+
reg = <0x10003000 0x1000>;
57+
#clock-cells = <1>;
58+
};
59+
60+
- |
61+
apmixedsys: syscon@1000c000 {
62+
compatible = "mediatek,mt8192-apmixedsys", "syscon";
63+
reg = <0x1000c000 0x1000>;
64+
#clock-cells = <1>;
65+
};

‎Documentation/devicetree/bindings/clock/qcom,a53pll.yaml

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -18,6 +18,7 @@ properties:
1818
enum:
1919
- qcom,ipq6018-a53pll
2020
- qcom,msm8916-a53pll
21+
- qcom,msm8939-a53pll
2122

2223
reg:
2324
maxItems: 1
@@ -33,6 +34,8 @@ properties:
3334
items:
3435
- const: xo
3536

37+
operating-points-v2: true
38+
3639
required:
3740
- compatible
3841
- reg

‎Documentation/devicetree/bindings/clock/qcom,gcc-sm6115.yaml

Lines changed: 72 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,72 @@
1+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2+
%YAML 1.2
3+
---
4+
$id: http://devicetree.org/schemas/clock/qcom,gcc-sm6115.yaml#
5+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6+
7+
title: Qualcomm Global Clock & Reset Controller Binding for SM6115 and SM4250
8+
9+
maintainers:
10+
- Iskren Chernev <[email protected]>
11+
12+
description: |
13+
Qualcomm global clock control module which supports the clocks, resets and
14+
power domains on SM4250/6115.
15+
16+
See also:
17+
- dt-bindings/clock/qcom,gcc-sm6115.h
18+
19+
properties:
20+
compatible:
21+
const: qcom,gcc-sm6115
22+
23+
clocks:
24+
items:
25+
- description: Board XO source
26+
- description: Sleep clock source
27+
28+
clock-names:
29+
items:
30+
- const: bi_tcxo
31+
- const: sleep_clk
32+
33+
'#clock-cells':
34+
const: 1
35+
36+
'#reset-cells':
37+
const: 1
38+
39+
'#power-domain-cells':
40+
const: 1
41+
42+
reg:
43+
maxItems: 1
44+
45+
protected-clocks:
46+
description:
47+
Protected clock specifier list as per common clock binding.
48+
49+
required:
50+
- compatible
51+
- clocks
52+
- clock-names
53+
- reg
54+
- '#clock-cells'
55+
- '#reset-cells'
56+
- '#power-domain-cells'
57+
58+
additionalProperties: false
59+
60+
examples:
61+
- |
62+
#include <dt-bindings/clock/qcom,rpmcc.h>
63+
clock-controller@1400000 {
64+
compatible = "qcom,gcc-sm6115";
65+
reg = <0x01400000 0x1f0000>;
66+
#clock-cells = <1>;
67+
#reset-cells = <1>;
68+
#power-domain-cells = <1>;
69+
clock-names = "bi_tcxo", "sleep_clk";
70+
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&sleep_clk>;
71+
};
72+
...

0 commit comments

Comments
 (0)