@@ -42,6 +42,11 @@ Required properties:
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"idlest" - contains the idle status register base address
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"mult-div1" - contains the multiplier / divider register base address
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"autoidle" - contains the autoidle register base address (optional)
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+ "ssc-deltam" - DPLL supports spread spectrum clocking (SSC), contains
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+ the frequency spreading register base address (optional)
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+ "ssc-modfreq" - DPLL supports spread spectrum clocking (SSC), contains
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+ the modulation frequency register base address
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+ (optional)
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ti,am3-* dpll types do not have autoidle register
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ti,omap2-* dpll type does not support idlest / autoidle registers
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@@ -51,6 +56,14 @@ Optional properties:
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- ti,low-power-stop : DPLL supports low power stop mode, gating output
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- ti,low-power-bypass : DPLL output matches rate of parent bypass clock
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- ti,lock : DPLL locks in programmed rate
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+ - ti,min-div : the minimum divisor to start from to round the DPLL
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+ target rate
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+ - ti,ssc-deltam : DPLL supports spread spectrum clocking, frequency
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+ spreading in permille (10th of a percent)
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+ - ti,ssc-modfreq-hz : DPLL supports spread spectrum clocking, spread
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+ spectrum modulation frequency
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+ - ti,ssc-downspread : DPLL supports spread spectrum clocking, boolean
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+ to enable the downspread feature
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Examples:
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dpll_core_ck: dpll_core_ck@44e00490 {
@@ -83,3 +96,10 @@ Examples:
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clocks = <&sys_ck>, <&sys_ck>;
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reg = <0x0500>, <0x0540>;
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};
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+
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+ dpll_disp_ck: dpll_disp_ck {
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+ #clock-cells = <0>;
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+ compatible = "ti,am3-dpll-no-gate-clock";
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+ clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
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+ reg = <0x0498>, <0x0448>, <0x0454>, <0x044c>, <0x0450>;
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+ };
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