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Merge tag 'iommu-fixes-v5.15-rc0' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu
Pull iommu fixes from Joerg Roedel: - Intel VT-d: - PASID leakage in intel_svm_unbind_mm() - Deadlock in intel_svm_drain_prq() - AMD IOMMU: Fixes for an unhandled page-fault bug when AVIC is used for a KVM guest. - Make CONFIG_IOMMU_DEFAULT_DMA_LAZY architecture instead of IOMMU driver dependent * tag 'iommu-fixes-v5.15-rc0' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu: iommu: Clarify default domain Kconfig iommu/vt-d: Fix a deadlock in intel_svm_drain_prq() iommu/vt-d: Fix PASID leak in intel_svm_unbind_mm() iommu/amd: Remove iommu_init_ga() iommu/amd: Relocate GAMSup check to early_enable_iommus
2 parents 5ffc06e + 8cc6331 commit 589e5ca

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-24
lines changed

3 files changed

+41
-24
lines changed

drivers/iommu/Kconfig

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -82,7 +82,7 @@ config IOMMU_DEBUGFS
8282
choice
8383
prompt "IOMMU default domain type"
8484
depends on IOMMU_API
85-
default IOMMU_DEFAULT_DMA_LAZY if AMD_IOMMU || INTEL_IOMMU
85+
default IOMMU_DEFAULT_DMA_LAZY if X86 || IA64
8686
default IOMMU_DEFAULT_DMA_STRICT
8787
help
8888
Choose the type of IOMMU domain used to manage DMA API usage by

drivers/iommu/amd/init.c

Lines changed: 28 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -297,6 +297,22 @@ int amd_iommu_get_num_iommus(void)
297297
return amd_iommus_present;
298298
}
299299

300+
#ifdef CONFIG_IRQ_REMAP
301+
static bool check_feature_on_all_iommus(u64 mask)
302+
{
303+
bool ret = false;
304+
struct amd_iommu *iommu;
305+
306+
for_each_iommu(iommu) {
307+
ret = iommu_feature(iommu, mask);
308+
if (!ret)
309+
return false;
310+
}
311+
312+
return true;
313+
}
314+
#endif
315+
300316
/*
301317
* For IVHD type 0x11/0x40, EFR is also available via IVHD.
302318
* Default to IVHD EFR since it is available sooner
@@ -813,9 +829,9 @@ static int iommu_ga_log_enable(struct amd_iommu *iommu)
813829
return 0;
814830
}
815831

816-
#ifdef CONFIG_IRQ_REMAP
817832
static int iommu_init_ga_log(struct amd_iommu *iommu)
818833
{
834+
#ifdef CONFIG_IRQ_REMAP
819835
u64 entry;
820836

821837
if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir))
@@ -845,25 +861,9 @@ static int iommu_init_ga_log(struct amd_iommu *iommu)
845861
err_out:
846862
free_ga_log(iommu);
847863
return -EINVAL;
848-
}
849-
#endif /* CONFIG_IRQ_REMAP */
850-
851-
static int iommu_init_ga(struct amd_iommu *iommu)
852-
{
853-
int ret = 0;
854-
855-
#ifdef CONFIG_IRQ_REMAP
856-
/* Note: We have already checked GASup from IVRS table.
857-
* Now, we need to make sure that GAMSup is set.
858-
*/
859-
if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) &&
860-
!iommu_feature(iommu, FEATURE_GAM_VAPIC))
861-
amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY_GA;
862-
863-
ret = iommu_init_ga_log(iommu);
864+
#else
865+
return 0;
864866
#endif /* CONFIG_IRQ_REMAP */
865-
866-
return ret;
867867
}
868868

869869
static int __init alloc_cwwb_sem(struct amd_iommu *iommu)
@@ -1845,7 +1845,7 @@ static int __init iommu_init_pci(struct amd_iommu *iommu)
18451845
if (iommu_feature(iommu, FEATURE_PPR) && alloc_ppr_log(iommu))
18461846
return -ENOMEM;
18471847

1848-
ret = iommu_init_ga(iommu);
1848+
ret = iommu_init_ga_log(iommu);
18491849
if (ret)
18501850
return ret;
18511851

@@ -2479,6 +2479,14 @@ static void early_enable_iommus(void)
24792479
}
24802480

24812481
#ifdef CONFIG_IRQ_REMAP
2482+
/*
2483+
* Note: We have already checked GASup from IVRS table.
2484+
* Now, we need to make sure that GAMSup is set.
2485+
*/
2486+
if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) &&
2487+
!check_feature_on_all_iommus(FEATURE_GAM_VAPIC))
2488+
amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY_GA;
2489+
24822490
if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir))
24832491
amd_iommu_irq_ops.capability |= (1 << IRQ_POSTING_CAP);
24842492
#endif

drivers/iommu/intel/svm.c

Lines changed: 12 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -514,9 +514,6 @@ static void load_pasid(struct mm_struct *mm, u32 pasid)
514514
{
515515
mutex_lock(&mm->context.lock);
516516

517-
/* Synchronize with READ_ONCE in update_pasid(). */
518-
smp_store_release(&mm->pasid, pasid);
519-
520517
/* Update PASID MSR on all CPUs running the mm's tasks. */
521518
on_each_cpu_mask(mm_cpumask(mm), _load_pasid, NULL, true);
522519

@@ -792,7 +789,19 @@ static void intel_svm_drain_prq(struct device *dev, u32 pasid)
792789
goto prq_retry;
793790
}
794791

792+
/*
793+
* A work in IO page fault workqueue may try to lock pasid_mutex now.
794+
* Holding pasid_mutex while waiting in iopf_queue_flush_dev() for
795+
* all works in the workqueue to finish may cause deadlock.
796+
*
797+
* It's unnecessary to hold pasid_mutex in iopf_queue_flush_dev().
798+
* Unlock it to allow the works to be handled while waiting for
799+
* them to finish.
800+
*/
801+
lockdep_assert_held(&pasid_mutex);
802+
mutex_unlock(&pasid_mutex);
795803
iopf_queue_flush_dev(dev);
804+
mutex_lock(&pasid_mutex);
796805

797806
/*
798807
* Perform steps described in VT-d spec CH7.10 to drain page

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