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Krishna Manikandanrobclark
Krishna Manikandan
authored and
robclark
committed
drm/msm/disp/dpu1: add support for display for SC7280 target
Add required display hw catalog changes for SC7280 target. Signed-off-by: Krishna Manikandan <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Rob Clark <[email protected]>
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-18
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5 files changed

+171
-18
lines changed

‎drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c

Lines changed: 160 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -43,6 +43,9 @@
4343
#define PINGPONG_SDM845_SPLIT_MASK \
4444
(PINGPONG_SDM845_MASK | BIT(DPU_PINGPONG_TE2))
4545

46+
#define CTL_SC7280_MASK \
47+
(BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_FETCH_ACTIVE))
48+
4649
#define MERGE_3D_SM8150_MASK (0)
4750

4851
#define DSPP_SC7180_MASK BIT(DPU_DSPP_PCC)
@@ -51,6 +54,8 @@
5154

5255
#define INTF_SC7180_MASK BIT(DPU_INTF_INPUT_CTRL) | BIT(DPU_INTF_TE)
5356

57+
#define INTF_SC7280_MASK INTF_SC7180_MASK | BIT(DPU_DATA_HCTL_EN)
58+
5459
#define DEFAULT_PIXEL_RAM_SIZE (50 * 1024)
5560
#define DEFAULT_DPU_LINE_WIDTH 2048
5661
#define DEFAULT_DPU_OUTPUT_LINE_WIDTH 2560
@@ -199,6 +204,18 @@ static const struct dpu_caps sm8250_dpu_caps = {
199204
.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
200205
};
201206

207+
static const struct dpu_caps sc7280_dpu_caps = {
208+
.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
209+
.max_mixer_blendstages = 0x7,
210+
.qseed_type = DPU_SSPP_SCALER_QSEED4,
211+
.smart_dma_rev = DPU_SSPP_SMART_DMA_V2,
212+
.ubwc_version = DPU_HW_UBWC_VER_30,
213+
.has_dim_layer = true,
214+
.has_idle_pc = true,
215+
.max_linewidth = 2400,
216+
.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
217+
};
218+
202219
static const struct dpu_mdp_cfg sdm845_mdp[] = {
203220
{
204221
.name = "top_0", .id = MDP_TOP,
@@ -268,6 +285,22 @@ static const struct dpu_mdp_cfg sm8250_mdp[] = {
268285
},
269286
};
270287

288+
static const struct dpu_mdp_cfg sc7280_mdp[] = {
289+
{
290+
.name = "top_0", .id = MDP_TOP,
291+
.base = 0x0, .len = 0x2014,
292+
.highest_bank_bit = 0x1,
293+
.clk_ctrls[DPU_CLK_CTRL_VIG0] = {
294+
.reg_off = 0x2AC, .bit_off = 0},
295+
.clk_ctrls[DPU_CLK_CTRL_DMA0] = {
296+
.reg_off = 0x2AC, .bit_off = 8},
297+
.clk_ctrls[DPU_CLK_CTRL_CURSOR0] = {
298+
.reg_off = 0x2B4, .bit_off = 8},
299+
.clk_ctrls[DPU_CLK_CTRL_CURSOR1] = {
300+
.reg_off = 0x2C4, .bit_off = 8},
301+
},
302+
};
303+
271304
/*************************************************************
272305
* CTL sub blocks config
273306
*************************************************************/
@@ -350,6 +383,29 @@ static const struct dpu_ctl_cfg sm8150_ctl[] = {
350383
},
351384
};
352385

386+
static const struct dpu_ctl_cfg sc7280_ctl[] = {
387+
{
388+
.name = "ctl_0", .id = CTL_0,
389+
.base = 0x15000, .len = 0x1E8,
390+
.features = CTL_SC7280_MASK
391+
},
392+
{
393+
.name = "ctl_1", .id = CTL_1,
394+
.base = 0x16000, .len = 0x1E8,
395+
.features = CTL_SC7280_MASK
396+
},
397+
{
398+
.name = "ctl_2", .id = CTL_2,
399+
.base = 0x17000, .len = 0x1E8,
400+
.features = CTL_SC7280_MASK
401+
},
402+
{
403+
.name = "ctl_3", .id = CTL_3,
404+
.base = 0x18000, .len = 0x1E8,
405+
.features = CTL_SC7280_MASK
406+
},
407+
};
408+
353409
/*************************************************************
354410
* SSPP sub blocks config
355411
*************************************************************/
@@ -475,6 +531,17 @@ static const struct dpu_sspp_cfg sm8250_sspp[] = {
475531
sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1),
476532
};
477533

534+
static const struct dpu_sspp_cfg sc7280_sspp[] = {
535+
SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_SC7180_MASK,
536+
sc7180_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
537+
SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_SDM845_MASK,
538+
sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
539+
SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, DMA_CURSOR_SDM845_MASK,
540+
sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0),
541+
SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, DMA_CURSOR_SDM845_MASK,
542+
sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1),
543+
};
544+
478545
/*************************************************************
479546
* MIXER sub blocks config
480547
*************************************************************/
@@ -550,6 +617,15 @@ static const struct dpu_lm_cfg sm8150_lm[] = {
550617
&sdm845_lm_sblk, PINGPONG_5, LM_4, 0),
551618
};
552619

620+
static const struct dpu_lm_cfg sc7280_lm[] = {
621+
LM_BLK("lm_0", LM_0, 0x44000, MIXER_SC7180_MASK,
622+
&sc7180_lm_sblk, PINGPONG_0, 0, 0),
623+
LM_BLK("lm_2", LM_2, 0x46000, MIXER_SC7180_MASK,
624+
&sc7180_lm_sblk, PINGPONG_2, LM_3, 0),
625+
LM_BLK("lm_3", LM_3, 0x47000, MIXER_SC7180_MASK,
626+
&sc7180_lm_sblk, PINGPONG_3, LM_2, 0),
627+
};
628+
553629
/*************************************************************
554630
* DSPP sub blocks config
555631
*************************************************************/
@@ -602,42 +678,47 @@ static const struct dpu_pingpong_sub_blks sdm845_pp_sblk = {
602678
.len = 0x20, .version = 0x10000},
603679
};
604680

605-
#define PP_BLK_TE(_name, _id, _base, _merge_3d) \
681+
static const struct dpu_pingpong_sub_blks sc7280_pp_sblk = {
682+
.dither = {.id = DPU_PINGPONG_DITHER, .base = 0xe0,
683+
.len = 0x20, .version = 0x20000},
684+
};
685+
686+
#define PP_BLK_TE(_name, _id, _base, _merge_3d, _sblk) \
606687
{\
607688
.name = _name, .id = _id, \
608689
.base = _base, .len = 0xd4, \
609690
.features = PINGPONG_SDM845_SPLIT_MASK, \
610691
.merge_3d = _merge_3d, \
611-
.sblk = &sdm845_pp_sblk_te \
692+
.sblk = &_sblk \
612693
}
613-
#define PP_BLK(_name, _id, _base, _merge_3d) \
694+
#define PP_BLK(_name, _id, _base, _merge_3d, _sblk) \
614695
{\
615696
.name = _name, .id = _id, \
616697
.base = _base, .len = 0xd4, \
617698
.features = PINGPONG_SDM845_MASK, \
618699
.merge_3d = _merge_3d, \
619-
.sblk = &sdm845_pp_sblk \
700+
.sblk = &_sblk \
620701
}
621702

622703
static const struct dpu_pingpong_cfg sdm845_pp[] = {
623-
PP_BLK_TE("pingpong_0", PINGPONG_0, 0x70000, 0),
624-
PP_BLK_TE("pingpong_1", PINGPONG_1, 0x70800, 0),
625-
PP_BLK("pingpong_2", PINGPONG_2, 0x71000, 0),
626-
PP_BLK("pingpong_3", PINGPONG_3, 0x71800, 0),
704+
PP_BLK_TE("pingpong_0", PINGPONG_0, 0x70000, 0, sdm845_pp_sblk_te),
705+
PP_BLK_TE("pingpong_1", PINGPONG_1, 0x70800, 0, sdm845_pp_sblk_te),
706+
PP_BLK("pingpong_2", PINGPONG_2, 0x71000, 0, sdm845_pp_sblk),
707+
PP_BLK("pingpong_3", PINGPONG_3, 0x71800, 0, sdm845_pp_sblk),
627708
};
628709

629710
static struct dpu_pingpong_cfg sc7180_pp[] = {
630-
PP_BLK_TE("pingpong_0", PINGPONG_0, 0x70000, 0),
631-
PP_BLK_TE("pingpong_1", PINGPONG_1, 0x70800, 0),
711+
PP_BLK_TE("pingpong_0", PINGPONG_0, 0x70000, 0, sdm845_pp_sblk_te),
712+
PP_BLK_TE("pingpong_1", PINGPONG_1, 0x70800, 0, sdm845_pp_sblk_te),
632713
};
633714

634715
static const struct dpu_pingpong_cfg sm8150_pp[] = {
635-
PP_BLK_TE("pingpong_0", PINGPONG_0, 0x70000, MERGE_3D_0),
636-
PP_BLK_TE("pingpong_1", PINGPONG_1, 0x70800, MERGE_3D_0),
637-
PP_BLK("pingpong_2", PINGPONG_2, 0x71000, MERGE_3D_1),
638-
PP_BLK("pingpong_3", PINGPONG_3, 0x71800, MERGE_3D_1),
639-
PP_BLK("pingpong_4", PINGPONG_4, 0x72000, MERGE_3D_2),
640-
PP_BLK("pingpong_5", PINGPONG_5, 0x72800, MERGE_3D_2),
716+
PP_BLK_TE("pingpong_0", PINGPONG_0, 0x70000, MERGE_3D_0, sdm845_pp_sblk_te),
717+
PP_BLK_TE("pingpong_1", PINGPONG_1, 0x70800, MERGE_3D_0, sdm845_pp_sblk_te),
718+
PP_BLK("pingpong_2", PINGPONG_2, 0x71000, MERGE_3D_1, sdm845_pp_sblk),
719+
PP_BLK("pingpong_3", PINGPONG_3, 0x71800, MERGE_3D_1, sdm845_pp_sblk),
720+
PP_BLK("pingpong_4", PINGPONG_4, 0x72000, MERGE_3D_2, sdm845_pp_sblk),
721+
PP_BLK("pingpong_5", PINGPONG_5, 0x72800, MERGE_3D_2, sdm845_pp_sblk),
641722
};
642723

643724
/*************************************************************
@@ -657,6 +738,12 @@ static const struct dpu_merge_3d_cfg sm8150_merge_3d[] = {
657738
MERGE_3D_BLK("merge_3d_2", MERGE_3D_2, 0x83200),
658739
};
659740

741+
static const struct dpu_pingpong_cfg sc7280_pp[] = {
742+
PP_BLK("pingpong_0", PINGPONG_0, 0x59000, 0, sc7280_pp_sblk),
743+
PP_BLK("pingpong_1", PINGPONG_1, 0x6a000, 0, sc7280_pp_sblk),
744+
PP_BLK("pingpong_2", PINGPONG_2, 0x6b000, 0, sc7280_pp_sblk),
745+
PP_BLK("pingpong_3", PINGPONG_3, 0x6c000, 0, sc7280_pp_sblk),
746+
};
660747
/*************************************************************
661748
* INTF sub blocks config
662749
*************************************************************/
@@ -689,6 +776,12 @@ static const struct dpu_intf_cfg sm8150_intf[] = {
689776
INTF_BLK("intf_3", INTF_3, 0x6B800, INTF_DP, 1, 24, INTF_SC7180_MASK),
690777
};
691778

779+
static const struct dpu_intf_cfg sc7280_intf[] = {
780+
INTF_BLK("intf_0", INTF_0, 0x34000, INTF_DP, 0, 24, INTF_SC7280_MASK),
781+
INTF_BLK("intf_1", INTF_1, 0x35000, INTF_DSI, 0, 24, INTF_SC7280_MASK),
782+
INTF_BLK("intf_5", INTF_5, 0x39000, INTF_EDP, 0, 24, INTF_SC7280_MASK),
783+
};
784+
692785
/*************************************************************
693786
* VBIF sub blocks config
694787
*************************************************************/
@@ -904,6 +997,33 @@ static const struct dpu_perf_cfg sm8250_perf_data = {
904997
.bw_inefficiency_factor = 120,
905998
};
906999

1000+
static const struct dpu_perf_cfg sc7280_perf_data = {
1001+
.max_bw_low = 4700000,
1002+
.max_bw_high = 8800000,
1003+
.min_core_ib = 2500000,
1004+
.min_llcc_ib = 0,
1005+
.min_dram_ib = 1600000,
1006+
.min_prefill_lines = 24,
1007+
.danger_lut_tbl = {0xffff, 0xffff, 0x0},
1008+
.qos_lut_tbl = {
1009+
{.nentry = ARRAY_SIZE(sc7180_qos_macrotile),
1010+
.entries = sc7180_qos_macrotile
1011+
},
1012+
{.nentry = ARRAY_SIZE(sc7180_qos_macrotile),
1013+
.entries = sc7180_qos_macrotile
1014+
},
1015+
{.nentry = ARRAY_SIZE(sc7180_qos_nrt),
1016+
.entries = sc7180_qos_nrt
1017+
},
1018+
},
1019+
.cdp_cfg = {
1020+
{.rd_enable = 1, .wr_enable = 1},
1021+
{.rd_enable = 1, .wr_enable = 0}
1022+
},
1023+
.clk_inefficiency_factor = 105,
1024+
.bw_inefficiency_factor = 120,
1025+
};
1026+
9071027
/*************************************************************
9081028
* Hardware catalog init
9091029
*************************************************************/
@@ -1034,13 +1154,37 @@ static void sm8250_cfg_init(struct dpu_mdss_cfg *dpu_cfg)
10341154
};
10351155
}
10361156

1157+
static void sc7280_cfg_init(struct dpu_mdss_cfg *dpu_cfg)
1158+
{
1159+
*dpu_cfg = (struct dpu_mdss_cfg){
1160+
.caps = &sc7280_dpu_caps,
1161+
.mdp_count = ARRAY_SIZE(sc7280_mdp),
1162+
.mdp = sc7280_mdp,
1163+
.ctl_count = ARRAY_SIZE(sc7280_ctl),
1164+
.ctl = sc7280_ctl,
1165+
.sspp_count = ARRAY_SIZE(sc7280_sspp),
1166+
.sspp = sc7280_sspp,
1167+
.mixer_count = ARRAY_SIZE(sc7280_lm),
1168+
.mixer = sc7280_lm,
1169+
.pingpong_count = ARRAY_SIZE(sc7280_pp),
1170+
.pingpong = sc7280_pp,
1171+
.intf_count = ARRAY_SIZE(sc7280_intf),
1172+
.intf = sc7280_intf,
1173+
.vbif_count = ARRAY_SIZE(sdm845_vbif),
1174+
.vbif = sdm845_vbif,
1175+
.perf = sc7280_perf_data,
1176+
.mdss_irqs = 0x1c07,
1177+
};
1178+
}
1179+
10371180
static const struct dpu_mdss_hw_cfg_handler cfg_handler[] = {
10381181
{ .hw_rev = DPU_HW_VER_400, .cfg_init = sdm845_cfg_init},
10391182
{ .hw_rev = DPU_HW_VER_401, .cfg_init = sdm845_cfg_init},
10401183
{ .hw_rev = DPU_HW_VER_500, .cfg_init = sm8150_cfg_init},
10411184
{ .hw_rev = DPU_HW_VER_501, .cfg_init = sm8150_cfg_init},
10421185
{ .hw_rev = DPU_HW_VER_600, .cfg_init = sm8250_cfg_init},
10431186
{ .hw_rev = DPU_HW_VER_620, .cfg_init = sc7180_cfg_init},
1187+
{ .hw_rev = DPU_HW_VER_720, .cfg_init = sc7280_cfg_init},
10441188
};
10451189

10461190
void dpu_hw_catalog_deinit(struct dpu_mdss_cfg *dpu_cfg)

‎drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h

Lines changed: 6 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -41,15 +41,15 @@
4141
#define DPU_HW_VER_501 DPU_HW_VER(5, 0, 1) /* sm8150 v2.0 */
4242
#define DPU_HW_VER_600 DPU_HW_VER(6, 0, 0) /* sm8250 */
4343
#define DPU_HW_VER_620 DPU_HW_VER(6, 2, 0) /* sc7180 v1.0 */
44-
44+
#define DPU_HW_VER_720 DPU_HW_VER(7, 2, 0) /* sc7280 */
4545

4646
#define IS_MSM8996_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_170)
4747
#define IS_MSM8998_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_300)
4848
#define IS_SDM845_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_400)
4949
#define IS_SDM670_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_410)
5050
#define IS_SDM855_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_500)
5151
#define IS_SC7180_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_620)
52-
52+
#define IS_SC7280_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_720)
5353

5454
#define DPU_HW_BLK_NAME_LEN 16
5555

@@ -185,6 +185,7 @@ enum {
185185
enum {
186186
DPU_CTL_SPLIT_DISPLAY = 0x1,
187187
DPU_CTL_ACTIVE_CFG,
188+
DPU_CTL_FETCH_ACTIVE,
188189
DPU_CTL_MAX
189190
};
190191

@@ -193,11 +194,14 @@ enum {
193194
* @DPU_INTF_INPUT_CTRL Supports the setting of pp block from which
194195
* pixel data arrives to this INTF
195196
* @DPU_INTF_TE INTF block has TE configuration support
197+
* @DPU_DATA_HCTL_EN Allows data to be transferred at different rate
198+
than video timing
196199
* @DPU_INTF_MAX
197200
*/
198201
enum {
199202
DPU_INTF_INPUT_CTRL = 0x1,
200203
DPU_INTF_TE,
204+
DPU_DATA_HCTL_EN,
201205
DPU_INTF_MAX
202206
};
203207

‎drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1225,6 +1225,7 @@ static const struct dev_pm_ops dpu_pm_ops = {
12251225
static const struct of_device_id dpu_dt_match[] = {
12261226
{ .compatible = "qcom,sdm845-dpu", },
12271227
{ .compatible = "qcom,sc7180-dpu", },
1228+
{ .compatible = "qcom,sc7280-dpu", },
12281229
{ .compatible = "qcom,sm8150-dpu", },
12291230
{ .compatible = "qcom,sm8250-dpu", },
12301231
{}

‎drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -170,6 +170,9 @@ static int dpu_mdss_enable(struct msm_mdss *mdss)
170170
case DPU_HW_VER_620:
171171
writel_relaxed(0x1e, dpu_mdss->mmio + UBWC_STATIC);
172172
break;
173+
case DPU_HW_VER_720:
174+
writel_relaxed(0x101e, dpu_mdss->mmio + UBWC_STATIC);
175+
break;
173176
}
174177

175178
return ret;

‎drivers/gpu/drm/msm/msm_drv.c

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1341,6 +1341,7 @@ static const struct of_device_id dt_match[] = {
13411341
{ .compatible = "qcom,mdss", .data = (void *)KMS_MDP5 },
13421342
{ .compatible = "qcom,sdm845-mdss", .data = (void *)KMS_DPU },
13431343
{ .compatible = "qcom,sc7180-mdss", .data = (void *)KMS_DPU },
1344+
{ .compatible = "qcom,sc7280-mdss", .data = (void *)KMS_DPU },
13441345
{ .compatible = "qcom,sm8150-mdss", .data = (void *)KMS_DPU },
13451346
{ .compatible = "qcom,sm8250-mdss", .data = (void *)KMS_DPU },
13461347
{}

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