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bebarinobebarino
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Merge tag 'renesas-clk-for-v5.15-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas
Pull Renesas clk driver updates from Geert Uytterhoeven: - Add display (DU and DSI) clocks on R-Car V3U - Add I2C, DMAC, USB, sound (SSIF-2), GPIO, CANFD, and ADC clocks and resets on RZ/G2L - Miscellaneous fixes and improvements * tag 'renesas-clk-for-v5.15-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: clk: renesas: r9a07g044: Add entry for fixed clock P0_DIV2 dt-bindings: clock: r9a07g044-cpg: Add entry for P0_DIV2 core clock clk: renesas: r9a07g044: Add clock and reset entries for ADC clk: renesas: r9a07g044: Add clock and reset entries for CANFD clk: renesas: Rename renesas-rzg2l-cpg.[ch] to rzg2l-cpg.[ch] clk: renesas: r9a07g044: Add GPIO clock and reset entries clk: renesas: r9a07g044: Add SSIF-2 clock and reset entries clk: renesas: r9a07g044: Add USB clocks/resets clk: renesas: r9a07g044: Add DMAC clocks/resets clk: renesas: r9a07g044: Add I2C clocks/resets clk: renesas: r8a779a0: Add the DSI clocks clk: renesas: r8a779a0: Add the DU clock clk: renesas: rzg2: Rename i2c-dvfs to iic-pmic clk: renesas: rzg2l: Fix off-by-one check in rzg2l_cpg_clk_src_twocell_get() clk: renesas: rzg2l: Avoid mixing error pointers and NULL clk: renesas: rzg2l: Fix a double free on error clk: renesas: rzg2l: Fix return value and unused assignment clk: renesas: rzg2l: Remove unneeded semicolon
2 parents 2734d6c + d28b1e0 commit 5f1fc97

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10 files changed

+87
-23
lines changed

10 files changed

+87
-23
lines changed

‎drivers/clk/renesas/Makefile

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -37,7 +37,7 @@ obj-$(CONFIG_CLK_RCAR_CPG_LIB) += rcar-cpg-lib.o
3737
obj-$(CONFIG_CLK_RCAR_GEN2_CPG) += rcar-gen2-cpg.o
3838
obj-$(CONFIG_CLK_RCAR_GEN3_CPG) += rcar-gen3-cpg.o
3939
obj-$(CONFIG_CLK_RCAR_USB2_CLOCK_SEL) += rcar-usb2-clock-sel.o
40-
obj-$(CONFIG_CLK_RZG2L) += renesas-rzg2l-cpg.o
40+
obj-$(CONFIG_CLK_RZG2L) += rzg2l-cpg.o
4141

4242
# Generic
4343
obj-$(CONFIG_CLK_RENESAS_CPG_MSSR) += renesas-cpg-mssr.o

‎drivers/clk/renesas/r8a774a1-cpg-mssr.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -210,7 +210,7 @@ static const struct mssr_mod_clk r8a774a1_mod_clks[] __initconst = {
210210
DEF_MOD("rpc-if", 917, R8A774A1_CLK_RPCD2),
211211
DEF_MOD("i2c6", 918, R8A774A1_CLK_S0D6),
212212
DEF_MOD("i2c5", 919, R8A774A1_CLK_S0D6),
213-
DEF_MOD("i2c-dvfs", 926, R8A774A1_CLK_CP),
213+
DEF_MOD("iic-pmic", 926, R8A774A1_CLK_CP),
214214
DEF_MOD("i2c4", 927, R8A774A1_CLK_S0D6),
215215
DEF_MOD("i2c3", 928, R8A774A1_CLK_S0D6),
216216
DEF_MOD("i2c2", 929, R8A774A1_CLK_S3D2),

‎drivers/clk/renesas/r8a774b1-cpg-mssr.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -206,7 +206,7 @@ static const struct mssr_mod_clk r8a774b1_mod_clks[] __initconst = {
206206
DEF_MOD("rpc-if", 917, R8A774B1_CLK_RPCD2),
207207
DEF_MOD("i2c6", 918, R8A774B1_CLK_S0D6),
208208
DEF_MOD("i2c5", 919, R8A774B1_CLK_S0D6),
209-
DEF_MOD("i2c-dvfs", 926, R8A774B1_CLK_CP),
209+
DEF_MOD("iic-pmic", 926, R8A774B1_CLK_CP),
210210
DEF_MOD("i2c4", 927, R8A774B1_CLK_S0D6),
211211
DEF_MOD("i2c3", 928, R8A774B1_CLK_S0D6),
212212
DEF_MOD("i2c2", 929, R8A774B1_CLK_S3D2),

‎drivers/clk/renesas/r8a774c0-cpg-mssr.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -210,7 +210,7 @@ static const struct mssr_mod_clk r8a774c0_mod_clks[] __initconst = {
210210
DEF_MOD("rpc-if", 917, R8A774C0_CLK_RPCD2),
211211
DEF_MOD("i2c6", 918, R8A774C0_CLK_S3D2),
212212
DEF_MOD("i2c5", 919, R8A774C0_CLK_S3D2),
213-
DEF_MOD("i2c-dvfs", 926, R8A774C0_CLK_CP),
213+
DEF_MOD("iic-pmic", 926, R8A774C0_CLK_CP),
214214
DEF_MOD("i2c4", 927, R8A774C0_CLK_S3D2),
215215
DEF_MOD("i2c3", 928, R8A774C0_CLK_S3D2),
216216
DEF_MOD("i2c2", 929, R8A774C0_CLK_S3D2),

‎drivers/clk/renesas/r8a774e1-cpg-mssr.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -219,7 +219,7 @@ static const struct mssr_mod_clk r8a774e1_mod_clks[] __initconst = {
219219
DEF_MOD("i2c6", 918, R8A774E1_CLK_S0D6),
220220
DEF_MOD("i2c5", 919, R8A774E1_CLK_S0D6),
221221
DEF_MOD("adg", 922, R8A774E1_CLK_S0D1),
222-
DEF_MOD("i2c-dvfs", 926, R8A774E1_CLK_CP),
222+
DEF_MOD("iic-pmic", 926, R8A774E1_CLK_CP),
223223
DEF_MOD("i2c4", 927, R8A774E1_CLK_S0D6),
224224
DEF_MOD("i2c3", 928, R8A774E1_CLK_S0D6),
225225
DEF_MOD("i2c2", 929, R8A774E1_CLK_S3D2),

‎drivers/clk/renesas/r8a779a0-cpg-mssr.c

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -135,7 +135,6 @@ static const struct cpg_core_clk r8a779a0_core_clks[] __initconst = {
135135
DEF_FIXED("zt", R8A779A0_CLK_ZT, CLK_PLL1_DIV2, 2, 1),
136136
DEF_FIXED("ztr", R8A779A0_CLK_ZTR, CLK_PLL1_DIV2, 2, 1),
137137
DEF_FIXED("zr", R8A779A0_CLK_ZR, CLK_PLL1_DIV2, 1, 1),
138-
DEF_FIXED("dsi", R8A779A0_CLK_DSI, CLK_PLL5_DIV4, 1, 1),
139138
DEF_FIXED("cnndsp", R8A779A0_CLK_CNNDSP, CLK_PLL5_DIV4, 1, 1),
140139
DEF_FIXED("vip", R8A779A0_CLK_VIP, CLK_PLL5, 5, 1),
141140
DEF_FIXED("adgh", R8A779A0_CLK_ADGH, CLK_PLL5_DIV4, 1, 1),
@@ -151,6 +150,7 @@ static const struct cpg_core_clk r8a779a0_core_clks[] __initconst = {
151150
DEF_DIV6P1("mso", R8A779A0_CLK_MSO, CLK_PLL5_DIV4, 0x87c),
152151
DEF_DIV6P1("canfd", R8A779A0_CLK_CANFD, CLK_PLL5_DIV4, 0x878),
153152
DEF_DIV6P1("csi0", R8A779A0_CLK_CSI0, CLK_PLL5_DIV4, 0x880),
153+
DEF_DIV6P1("dsi", R8A779A0_CLK_DSI, CLK_PLL5_DIV4, 0x884),
154154

155155
DEF_OSC("osc", R8A779A0_CLK_OSC, CLK_EXTAL, 8),
156156
DEF_MDSEL("r", R8A779A0_CLK_R, 29, CLK_EXTALR, 1, CLK_OCO, 1),
@@ -167,6 +167,9 @@ static const struct mssr_mod_clk r8a779a0_mod_clks[] __initconst = {
167167
DEF_MOD("csi41", 400, R8A779A0_CLK_CSI0),
168168
DEF_MOD("csi42", 401, R8A779A0_CLK_CSI0),
169169
DEF_MOD("csi43", 402, R8A779A0_CLK_CSI0),
170+
DEF_MOD("du", 411, R8A779A0_CLK_S3D1),
171+
DEF_MOD("dsi0", 415, R8A779A0_CLK_DSI),
172+
DEF_MOD("dsi1", 416, R8A779A0_CLK_DSI),
170173
DEF_MOD("fcpvd0", 508, R8A779A0_CLK_S3D1),
171174
DEF_MOD("fcpvd1", 509, R8A779A0_CLK_S3D1),
172175
DEF_MOD("hscif0", 514, R8A779A0_CLK_S1D2),

‎drivers/clk/renesas/r9a07g044-cpg.c

Lines changed: 70 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -12,11 +12,11 @@
1212

1313
#include <dt-bindings/clock/r9a07g044-cpg.h>
1414

15-
#include "renesas-rzg2l-cpg.h"
15+
#include "rzg2l-cpg.h"
1616

1717
enum clk_ids {
1818
/* Core Clock Outputs exported to DT */
19-
LAST_DT_CORE_CLK = R9A07G044_OSCCLK,
19+
LAST_DT_CORE_CLK = R9A07G044_CLK_P0_DIV2,
2020

2121
/* External Input Clocks */
2222
CLK_EXTAL,
@@ -37,6 +37,7 @@ enum clk_ids {
3737
CLK_PLL5,
3838
CLK_PLL5_DIV2,
3939
CLK_PLL6,
40+
CLK_P1_DIV2,
4041

4142
/* Module Clocks */
4243
MOD_CLK_BASE,
@@ -76,9 +77,11 @@ static const struct cpg_core_clk r9a07g044_core_clks[] __initconst = {
7677
DEF_FIXED("I", R9A07G044_CLK_I, CLK_PLL1, 1, 1),
7778
DEF_DIV("P0", R9A07G044_CLK_P0, CLK_PLL2_DIV16, DIVPL2A,
7879
dtable_1_32, CLK_DIVIDER_HIWORD_MASK),
80+
DEF_FIXED("P0_DIV2", R9A07G044_CLK_P0_DIV2, R9A07G044_CLK_P0, 1, 2),
7981
DEF_FIXED("TSU", R9A07G044_CLK_TSU, CLK_PLL2_DIV20, 1, 1),
8082
DEF_DIV("P1", R9A07G044_CLK_P1, CLK_PLL3_DIV2_4,
8183
DIVPL3B, dtable_1_32, CLK_DIVIDER_HIWORD_MASK),
84+
DEF_FIXED("P1_DIV2", CLK_P1_DIV2, R9A07G044_CLK_P1, 1, 2),
8285
DEF_DIV("P2", R9A07G044_CLK_P2, CLK_PLL3_DIV2_4_2,
8386
DIVPL3A, dtable_1_32, CLK_DIVIDER_HIWORD_MASK),
8487
};
@@ -90,6 +93,42 @@ static struct rzg2l_mod_clk r9a07g044_mod_clks[] = {
9093
0x518, 0),
9194
DEF_MOD("ia55_clk", R9A07G044_IA55_CLK, R9A07G044_CLK_P1,
9295
0x518, 1),
96+
DEF_MOD("dmac_aclk", R9A07G044_DMAC_ACLK, R9A07G044_CLK_P1,
97+
0x52c, 0),
98+
DEF_MOD("dmac_pclk", R9A07G044_DMAC_PCLK, CLK_P1_DIV2,
99+
0x52c, 1),
100+
DEF_MOD("ssi0_pclk", R9A07G044_SSI0_PCLK2, R9A07G044_CLK_P0,
101+
0x570, 0),
102+
DEF_MOD("ssi0_sfr", R9A07G044_SSI0_PCLK_SFR, R9A07G044_CLK_P0,
103+
0x570, 1),
104+
DEF_MOD("ssi1_pclk", R9A07G044_SSI1_PCLK2, R9A07G044_CLK_P0,
105+
0x570, 2),
106+
DEF_MOD("ssi1_sfr", R9A07G044_SSI1_PCLK_SFR, R9A07G044_CLK_P0,
107+
0x570, 3),
108+
DEF_MOD("ssi2_pclk", R9A07G044_SSI2_PCLK2, R9A07G044_CLK_P0,
109+
0x570, 4),
110+
DEF_MOD("ssi2_sfr", R9A07G044_SSI2_PCLK_SFR, R9A07G044_CLK_P0,
111+
0x570, 5),
112+
DEF_MOD("ssi3_pclk", R9A07G044_SSI3_PCLK2, R9A07G044_CLK_P0,
113+
0x570, 6),
114+
DEF_MOD("ssi3_sfr", R9A07G044_SSI3_PCLK_SFR, R9A07G044_CLK_P0,
115+
0x570, 7),
116+
DEF_MOD("usb0_host", R9A07G044_USB_U2H0_HCLK, R9A07G044_CLK_P1,
117+
0x578, 0),
118+
DEF_MOD("usb1_host", R9A07G044_USB_U2H1_HCLK, R9A07G044_CLK_P1,
119+
0x578, 1),
120+
DEF_MOD("usb0_func", R9A07G044_USB_U2P_EXR_CPUCLK, R9A07G044_CLK_P1,
121+
0x578, 2),
122+
DEF_MOD("usb_pclk", R9A07G044_USB_PCLK, R9A07G044_CLK_P1,
123+
0x578, 3),
124+
DEF_MOD("i2c0", R9A07G044_I2C0_PCLK, R9A07G044_CLK_P0,
125+
0x580, 0),
126+
DEF_MOD("i2c1", R9A07G044_I2C1_PCLK, R9A07G044_CLK_P0,
127+
0x580, 1),
128+
DEF_MOD("i2c2", R9A07G044_I2C2_PCLK, R9A07G044_CLK_P0,
129+
0x580, 2),
130+
DEF_MOD("i2c3", R9A07G044_I2C3_PCLK, R9A07G044_CLK_P0,
131+
0x580, 3),
93132
DEF_MOD("scif0", R9A07G044_SCIF0_CLK_PCK, R9A07G044_CLK_P0,
94133
0x584, 0),
95134
DEF_MOD("scif1", R9A07G044_SCIF1_CLK_PCK, R9A07G044_CLK_P0,
@@ -102,18 +141,47 @@ static struct rzg2l_mod_clk r9a07g044_mod_clks[] = {
102141
0x584, 4),
103142
DEF_MOD("sci0", R9A07G044_SCI0_CLKP, R9A07G044_CLK_P0,
104143
0x588, 0),
144+
DEF_MOD("canfd", R9A07G044_CANFD_PCLK, R9A07G044_CLK_P0,
145+
0x594, 0),
146+
DEF_MOD("gpio", R9A07G044_GPIO_HCLK, R9A07G044_OSCCLK,
147+
0x598, 0),
148+
DEF_MOD("adc_adclk", R9A07G044_ADC_ADCLK, R9A07G044_CLK_TSU,
149+
0x5a8, 0),
150+
DEF_MOD("adc_pclk", R9A07G044_ADC_PCLK, R9A07G044_CLK_P0,
151+
0x5a8, 1),
105152
};
106153

107154
static struct rzg2l_reset r9a07g044_resets[] = {
108155
DEF_RST(R9A07G044_GIC600_GICRESET_N, 0x814, 0),
109156
DEF_RST(R9A07G044_GIC600_DBG_GICRESET_N, 0x814, 1),
110157
DEF_RST(R9A07G044_IA55_RESETN, 0x818, 0),
158+
DEF_RST(R9A07G044_DMAC_ARESETN, 0x82c, 0),
159+
DEF_RST(R9A07G044_DMAC_RST_ASYNC, 0x82c, 1),
160+
DEF_RST(R9A07G044_SSI0_RST_M2_REG, 0x870, 0),
161+
DEF_RST(R9A07G044_SSI1_RST_M2_REG, 0x870, 1),
162+
DEF_RST(R9A07G044_SSI2_RST_M2_REG, 0x870, 2),
163+
DEF_RST(R9A07G044_SSI3_RST_M2_REG, 0x870, 3),
164+
DEF_RST(R9A07G044_USB_U2H0_HRESETN, 0x878, 0),
165+
DEF_RST(R9A07G044_USB_U2H1_HRESETN, 0x878, 1),
166+
DEF_RST(R9A07G044_USB_U2P_EXL_SYSRST, 0x878, 2),
167+
DEF_RST(R9A07G044_USB_PRESETN, 0x878, 3),
168+
DEF_RST(R9A07G044_I2C0_MRST, 0x880, 0),
169+
DEF_RST(R9A07G044_I2C1_MRST, 0x880, 1),
170+
DEF_RST(R9A07G044_I2C2_MRST, 0x880, 2),
171+
DEF_RST(R9A07G044_I2C3_MRST, 0x880, 3),
111172
DEF_RST(R9A07G044_SCIF0_RST_SYSTEM_N, 0x884, 0),
112173
DEF_RST(R9A07G044_SCIF1_RST_SYSTEM_N, 0x884, 1),
113174
DEF_RST(R9A07G044_SCIF2_RST_SYSTEM_N, 0x884, 2),
114175
DEF_RST(R9A07G044_SCIF3_RST_SYSTEM_N, 0x884, 3),
115176
DEF_RST(R9A07G044_SCIF4_RST_SYSTEM_N, 0x884, 4),
116177
DEF_RST(R9A07G044_SCI0_RST, 0x888, 0),
178+
DEF_RST(R9A07G044_CANFD_RSTP_N, 0x894, 0),
179+
DEF_RST(R9A07G044_CANFD_RSTC_N, 0x894, 1),
180+
DEF_RST(R9A07G044_GPIO_RSTN, 0x898, 0),
181+
DEF_RST(R9A07G044_GPIO_PORT_RESETN, 0x898, 1),
182+
DEF_RST(R9A07G044_GPIO_SPARE_RESETN, 0x898, 2),
183+
DEF_RST(R9A07G044_ADC_PRESETN, 0x8a8, 0),
184+
DEF_RST(R9A07G044_ADC_ADRST_N, 0x8a8, 1),
117185
};
118186

119187
static const unsigned int r9a07g044_crit_mod_clks[] __initconst = {

‎drivers/clk/renesas/renesas-rzg2l-cpg.c renamed to ‎drivers/clk/renesas/rzg2l-cpg.c

Lines changed: 7 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -29,7 +29,7 @@
2929

3030
#include <dt-bindings/clock/renesas-cpg-mssr.h>
3131

32-
#include "renesas-rzg2l-cpg.h"
32+
#include "rzg2l-cpg.h"
3333

3434
#ifdef DEBUG
3535
#define WARN_DEBUG(x) WARN_ON(x)
@@ -125,7 +125,7 @@ rzg2l_cpg_div_clk_register(const struct cpg_core_clk *core,
125125
core->flag, &priv->rmw_lock);
126126

127127
if (IS_ERR(clk_hw))
128-
return NULL;
128+
return ERR_CAST(clk_hw);
129129

130130
return clk_hw->clk;
131131
}
@@ -175,17 +175,14 @@ rzg2l_cpg_pll_clk_register(const struct cpg_core_clk *core,
175175
struct clk_init_data init;
176176
const char *parent_name;
177177
struct pll_clk *pll_clk;
178-
struct clk *clk;
179178

180179
parent = clks[core->parent & 0xffff];
181180
if (IS_ERR(parent))
182181
return ERR_CAST(parent);
183182

184183
pll_clk = devm_kzalloc(dev, sizeof(*pll_clk), GFP_KERNEL);
185-
if (!pll_clk) {
186-
clk = ERR_PTR(-ENOMEM);
187-
return NULL;
188-
}
184+
if (!pll_clk)
185+
return ERR_PTR(-ENOMEM);
189186

190187
parent_name = __clk_get_name(parent);
191188
init.name = core->name;
@@ -200,11 +197,7 @@ rzg2l_cpg_pll_clk_register(const struct cpg_core_clk *core,
200197
pll_clk->priv = priv;
201198
pll_clk->type = core->type;
202199

203-
clk = clk_register(NULL, &pll_clk->hw);
204-
if (IS_ERR(clk))
205-
kfree(pll_clk);
206-
207-
return clk;
200+
return clk_register(NULL, &pll_clk->hw);
208201
}
209202

210203
static struct clk
@@ -229,7 +222,7 @@ static struct clk
229222

230223
case CPG_MOD:
231224
type = "module";
232-
if (clkidx > priv->num_mod_clks) {
225+
if (clkidx >= priv->num_mod_clks) {
233226
dev_err(dev, "Invalid %s clock index %u\n", type,
234227
clkidx);
235228
return ERR_PTR(-EINVAL);
@@ -297,7 +290,7 @@ rzg2l_cpg_register_core_clk(const struct cpg_core_clk *core,
297290
break;
298291
default:
299292
goto fail;
300-
};
293+
}
301294

302295
if (IS_ERR_OR_NULL(clk))
303296
goto fail;
@@ -473,7 +466,6 @@ rzg2l_cpg_register_mod_clk(const struct rzg2l_mod_clk *mod,
473466
fail:
474467
dev_err(dev, "Failed to register %s clock %s: %ld\n", "module",
475468
mod->name, PTR_ERR(clk));
476-
kfree(clock);
477469
}
478470

479471
#define rcdev_to_priv(x) container_of(x, struct rzg2l_cpg_priv, rcdev)

‎drivers/clk/renesas/renesas-rzg2l-cpg.h renamed to ‎drivers/clk/renesas/rzg2l-cpg.h

File renamed without changes.

‎include/dt-bindings/clock/r9a07g044-cpg.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -30,6 +30,7 @@
3030
#define R9A07G044_CLK_P2 19
3131
#define R9A07G044_CLK_AT 20
3232
#define R9A07G044_OSCCLK 21
33+
#define R9A07G044_CLK_P0_DIV2 22
3334

3435
/* R9A07G044 Module Clocks */
3536
#define R9A07G044_CA55_SCLK 0

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