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aknautiyaljnikula
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drm/dp_helper: Define options for FRL training for HDMI2.1 PCON
Currently the FRL training mode (Concurrent, Sequential) and training type (Normal, Extended) are not defined properly and are passed as bool values in drm_helpers for pcon configuration for FRL training. This patch: -Add register masks for Sequential and Normal FRL training options. -Fixes the drm_helpers for FRL Training configuration to use the appropriate masks. -Modifies the calls to the above drm_helpers in i915/intel_dp as per the above change. v2: Re-used the register masks for these options, instead of enum. (Ville) Signed-off-by: Ankit Nautiyal <[email protected]> Reviewed-by: Ville Syrjälä <[email protected]> Acked-by: Maxime Ripard <[email protected]> Signed-off-by: Jani Nikula <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
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-18
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drivers/gpu/drm/drm_dp_helper.c

Lines changed: 14 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -2635,14 +2635,16 @@ EXPORT_SYMBOL(drm_dp_pcon_is_frl_ready);
26352635
* drm_dp_pcon_frl_configure_1() - Set HDMI LINK Configuration-Step1
26362636
* @aux: DisplayPort AUX channel
26372637
* @max_frl_gbps: maximum frl bw to be configured between PCON and HDMI sink
2638-
* @concurrent_mode: true if concurrent mode or operation is required,
2639-
* false otherwise.
2638+
* @frl_mode: FRL Training mode, it can be either Concurrent or Sequential.
2639+
* In Concurrent Mode, the FRL link bring up can be done along with
2640+
* DP Link training. In Sequential mode, the FRL link bring up is done prior to
2641+
* the DP Link training.
26402642
*
26412643
* Returns 0 if success, else returns negative error code.
26422644
*/
26432645

26442646
int drm_dp_pcon_frl_configure_1(struct drm_dp_aux *aux, int max_frl_gbps,
2645-
bool concurrent_mode)
2647+
u8 frl_mode)
26462648
{
26472649
int ret;
26482650
u8 buf;
@@ -2651,7 +2653,7 @@ int drm_dp_pcon_frl_configure_1(struct drm_dp_aux *aux, int max_frl_gbps,
26512653
if (ret < 0)
26522654
return ret;
26532655

2654-
if (concurrent_mode)
2656+
if (frl_mode == DP_PCON_ENABLE_CONCURRENT_LINK)
26552657
buf |= DP_PCON_ENABLE_CONCURRENT_LINK;
26562658
else
26572659
buf &= ~DP_PCON_ENABLE_CONCURRENT_LINK;
@@ -2694,21 +2696,23 @@ EXPORT_SYMBOL(drm_dp_pcon_frl_configure_1);
26942696
* drm_dp_pcon_frl_configure_2() - Set HDMI Link configuration Step-2
26952697
* @aux: DisplayPort AUX channel
26962698
* @max_frl_mask : Max FRL BW to be tried by the PCON with HDMI Sink
2697-
* @extended_train_mode : true for Extended Mode, false for Normal Mode.
2698-
* In Normal mode, the PCON tries each frl bw from the max_frl_mask starting
2699-
* from min, and stops when link training is successful. In Extended mode, all
2700-
* frl bw selected in the mask are trained by the PCON.
2699+
* @frl_type : FRL training type, can be Extended, or Normal.
2700+
* In Normal FRL training, the PCON tries each frl bw from the max_frl_mask
2701+
* starting from min, and stops when link training is successful. In Extended
2702+
* FRL training, all frl bw selected in the mask are trained by the PCON.
27012703
*
27022704
* Returns 0 if success, else returns negative error code.
27032705
*/
27042706
int drm_dp_pcon_frl_configure_2(struct drm_dp_aux *aux, int max_frl_mask,
2705-
bool extended_train_mode)
2707+
u8 frl_type)
27062708
{
27072709
int ret;
27082710
u8 buf = max_frl_mask;
27092711

2710-
if (extended_train_mode)
2712+
if (frl_type == DP_PCON_FRL_LINK_TRAIN_EXTENDED)
27112713
buf |= DP_PCON_FRL_LINK_TRAIN_EXTENDED;
2714+
else
2715+
buf &= ~DP_PCON_FRL_LINK_TRAIN_EXTENDED;
27122716

27132717
ret = drm_dp_dpcd_writeb(aux, DP_PCON_HDMI_LINK_CONFIG_2, buf);
27142718
if (ret < 0)

drivers/gpu/drm/i915/display/intel_dp.c

Lines changed: 4 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -2073,10 +2073,6 @@ static int intel_dp_hdmi_sink_max_frl(struct intel_dp *intel_dp)
20732073

20742074
static int intel_dp_pcon_start_frl_training(struct intel_dp *intel_dp)
20752075
{
2076-
#define PCON_EXTENDED_TRAIN_MODE (1 > 0)
2077-
#define PCON_CONCURRENT_MODE (1 > 0)
2078-
#define PCON_SEQUENTIAL_MODE !PCON_CONCURRENT_MODE
2079-
#define PCON_NORMAL_TRAIN_MODE !PCON_EXTENDED_TRAIN_MODE
20802076
#define TIMEOUT_FRL_READY_MS 500
20812077
#define TIMEOUT_HDMI_LINK_ACTIVE_MS 1000
20822078

@@ -2110,10 +2106,12 @@ static int intel_dp_pcon_start_frl_training(struct intel_dp *intel_dp)
21102106
return -ETIMEDOUT;
21112107

21122108
max_frl_bw_mask = intel_dp_pcon_set_frl_mask(max_frl_bw);
2113-
ret = drm_dp_pcon_frl_configure_1(&intel_dp->aux, max_frl_bw, PCON_SEQUENTIAL_MODE);
2109+
ret = drm_dp_pcon_frl_configure_1(&intel_dp->aux, max_frl_bw,
2110+
DP_PCON_ENABLE_SEQUENTIAL_LINK);
21142111
if (ret < 0)
21152112
return ret;
2116-
ret = drm_dp_pcon_frl_configure_2(&intel_dp->aux, max_frl_bw_mask, PCON_NORMAL_TRAIN_MODE);
2113+
ret = drm_dp_pcon_frl_configure_2(&intel_dp->aux, max_frl_bw_mask,
2114+
DP_PCON_FRL_LINK_TRAIN_NORMAL);
21172115
if (ret < 0)
21182116
return ret;
21192117
ret = drm_dp_pcon_frl_enable(&intel_dp->aux);

include/drm/drm_dp_helper.h

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1176,6 +1176,7 @@ struct drm_device;
11761176
# define DP_PCON_ENABLE_MAX_BW_48GBPS 6
11771177
# define DP_PCON_ENABLE_SOURCE_CTL_MODE (1 << 3)
11781178
# define DP_PCON_ENABLE_CONCURRENT_LINK (1 << 4)
1179+
# define DP_PCON_ENABLE_SEQUENTIAL_LINK (0 << 4)
11791180
# define DP_PCON_ENABLE_LINK_FRL_MODE (1 << 5)
11801181
# define DP_PCON_ENABLE_HPD_READY (1 << 6)
11811182
# define DP_PCON_ENABLE_HDMI_LINK (1 << 7)
@@ -1190,6 +1191,7 @@ struct drm_device;
11901191
# define DP_PCON_FRL_BW_MASK_40GBPS (1 << 4)
11911192
# define DP_PCON_FRL_BW_MASK_48GBPS (1 << 5)
11921193
# define DP_PCON_FRL_LINK_TRAIN_EXTENDED (1 << 6)
1194+
# define DP_PCON_FRL_LINK_TRAIN_NORMAL (0 << 6)
11931195

11941196
/* PCON HDMI LINK STATUS */
11951197
#define DP_PCON_HDMI_TX_LINK_STATUS 0x303B
@@ -2154,9 +2156,9 @@ int drm_dp_get_pcon_max_frl_bw(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
21542156
int drm_dp_pcon_frl_prepare(struct drm_dp_aux *aux, bool enable_frl_ready_hpd);
21552157
bool drm_dp_pcon_is_frl_ready(struct drm_dp_aux *aux);
21562158
int drm_dp_pcon_frl_configure_1(struct drm_dp_aux *aux, int max_frl_gbps,
2157-
bool concurrent_mode);
2159+
u8 frl_mode);
21582160
int drm_dp_pcon_frl_configure_2(struct drm_dp_aux *aux, int max_frl_mask,
2159-
bool extended_train_mode);
2161+
u8 frl_type);
21602162
int drm_dp_pcon_reset_frl_config(struct drm_dp_aux *aux);
21612163
int drm_dp_pcon_frl_enable(struct drm_dp_aux *aux);
21622164

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