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Merge tag 'amd-drm-next-5.15-2021-08-20' of https://gitlab.freedesktop.org/agd5f/linux into drm-next
amd-drm-next-5.15-2021-08-20: amdgpu: - embed hw fence into job - Misc SMU fixes - PSP TA code cleanup - RAS fixes - PWM fan speed fixes - DC workqueue cleanups - SR-IOV fixes - gfxoff delayed work fix - Pin domain check fix amdkfd: - SVM fixes radeon: - Code cleanup Signed-off-by: Dave Airlie <[email protected]> From: Alex Deucher <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2 parents 397ab98 + 90a9266 commit 697b6e2

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‎drivers/gpu/drm/Kconfig

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -256,7 +256,6 @@ config DRM_AMDGPU
256256
select HWMON
257257
select BACKLIGHT_CLASS_DEVICE
258258
select INTERVAL_TREE
259-
select CHASH
260259
help
261260
Choose this option if you have a recent AMD Radeon graphics card.
262261

‎drivers/gpu/drm/amd/amdgpu/amdgpu.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1271,6 +1271,8 @@ int emu_soc_asic_init(struct amdgpu_device *adev);
12711271

12721272
#define amdgpu_inc_vram_lost(adev) atomic_inc(&((adev)->vram_lost_counter));
12731273

1274+
#define MIN(X, Y) ((X) < (Y) ? (X) : (Y))
1275+
12741276
/* Common functions */
12751277
bool amdgpu_device_has_job_running(struct amdgpu_device *adev);
12761278
bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev);

‎drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -714,7 +714,6 @@ int amdgpu_amdkfd_submit_ib(struct kgd_dev *kgd, enum kgd_engine_type engine,
714714
ret = dma_fence_wait(f, false);
715715

716716
err_ib_sched:
717-
dma_fence_put(f);
718717
amdgpu_job_free(job);
719718
err:
720719
return ret;

‎drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

Lines changed: 31 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -560,6 +560,9 @@ static int kgd_hqd_destroy(struct kgd_dev *kgd, void *mqd,
560560
case KFD_PREEMPT_TYPE_WAVEFRONT_RESET:
561561
type = RESET_WAVES;
562562
break;
563+
case KFD_PREEMPT_TYPE_WAVEFRONT_SAVE:
564+
type = SAVE_WAVES;
565+
break;
563566
default:
564567
type = DRAIN_PIPE;
565568
break;
@@ -754,6 +757,33 @@ static void set_vm_context_page_table_base(struct kgd_dev *kgd, uint32_t vmid,
754757
adev->gfxhub.funcs->setup_vm_pt_regs(adev, vmid, page_table_base);
755758
}
756759

760+
static void program_trap_handler_settings(struct kgd_dev *kgd,
761+
uint32_t vmid, uint64_t tba_addr, uint64_t tma_addr)
762+
{
763+
struct amdgpu_device *adev = get_amdgpu_device(kgd);
764+
765+
lock_srbm(kgd, 0, 0, 0, vmid);
766+
767+
/*
768+
* Program TBA registers
769+
*/
770+
WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_SHADER_TBA_LO),
771+
lower_32_bits(tba_addr >> 8));
772+
WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_SHADER_TBA_HI),
773+
upper_32_bits(tba_addr >> 8) |
774+
(1 << SQ_SHADER_TBA_HI__TRAP_EN__SHIFT));
775+
776+
/*
777+
* Program TMA registers
778+
*/
779+
WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_SHADER_TMA_LO),
780+
lower_32_bits(tma_addr >> 8));
781+
WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_SHADER_TMA_HI),
782+
upper_32_bits(tma_addr >> 8));
783+
784+
unlock_srbm(kgd);
785+
}
786+
757787
const struct kfd2kgd_calls gfx_v10_kfd2kgd = {
758788
.program_sh_mem_settings = kgd_program_sh_mem_settings,
759789
.set_pasid_vmid_mapping = kgd_set_pasid_vmid_mapping,
@@ -774,4 +804,5 @@ const struct kfd2kgd_calls gfx_v10_kfd2kgd = {
774804
.get_atc_vmid_pasid_mapping_info =
775805
get_atc_vmid_pasid_mapping_info,
776806
.set_vm_context_page_table_base = set_vm_context_page_table_base,
807+
.program_trap_handler_settings = program_trap_handler_settings,
777808
};

‎drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

Lines changed: 31 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -537,6 +537,9 @@ static int hqd_destroy_v10_3(struct kgd_dev *kgd, void *mqd,
537537
case KFD_PREEMPT_TYPE_WAVEFRONT_RESET:
538538
type = RESET_WAVES;
539539
break;
540+
case KFD_PREEMPT_TYPE_WAVEFRONT_SAVE:
541+
type = SAVE_WAVES;
542+
break;
540543
default:
541544
type = DRAIN_PIPE;
542545
break;
@@ -658,6 +661,33 @@ static void set_vm_context_page_table_base_v10_3(struct kgd_dev *kgd, uint32_t v
658661
adev->gfxhub.funcs->setup_vm_pt_regs(adev, vmid, page_table_base);
659662
}
660663

664+
static void program_trap_handler_settings_v10_3(struct kgd_dev *kgd,
665+
uint32_t vmid, uint64_t tba_addr, uint64_t tma_addr)
666+
{
667+
struct amdgpu_device *adev = get_amdgpu_device(kgd);
668+
669+
lock_srbm(kgd, 0, 0, 0, vmid);
670+
671+
/*
672+
* Program TBA registers
673+
*/
674+
WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_SHADER_TBA_LO),
675+
lower_32_bits(tba_addr >> 8));
676+
WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_SHADER_TBA_HI),
677+
upper_32_bits(tba_addr >> 8) |
678+
(1 << SQ_SHADER_TBA_HI__TRAP_EN__SHIFT));
679+
680+
/*
681+
* Program TMA registers
682+
*/
683+
WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_SHADER_TMA_LO),
684+
lower_32_bits(tma_addr >> 8));
685+
WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_SHADER_TMA_HI),
686+
upper_32_bits(tma_addr >> 8));
687+
688+
unlock_srbm(kgd);
689+
}
690+
661691
#if 0
662692
uint32_t enable_debug_trap_v10_3(struct kgd_dev *kgd,
663693
uint32_t trap_debug_wave_launch_mode,
@@ -820,6 +850,7 @@ const struct kfd2kgd_calls gfx_v10_3_kfd2kgd = {
820850
.address_watch_get_offset = address_watch_get_offset_v10_3,
821851
.get_atc_vmid_pasid_mapping_info = NULL,
822852
.set_vm_context_page_table_base = set_vm_context_page_table_base_v10_3,
853+
.program_trap_handler_settings = program_trap_handler_settings_v10_3,
823854
#if 0
824855
.enable_debug_trap = enable_debug_trap_v10_3,
825856
.disable_debug_trap = disable_debug_trap_v10_3,

‎drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

Lines changed: 32 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -42,7 +42,8 @@
4242
enum hqd_dequeue_request_type {
4343
NO_ACTION = 0,
4444
DRAIN_PIPE,
45-
RESET_WAVES
45+
RESET_WAVES,
46+
SAVE_WAVES
4647
};
4748

4849
static inline struct amdgpu_device *get_amdgpu_device(struct kgd_dev *kgd)
@@ -566,6 +567,9 @@ int kgd_gfx_v9_hqd_destroy(struct kgd_dev *kgd, void *mqd,
566567
case KFD_PREEMPT_TYPE_WAVEFRONT_RESET:
567568
type = RESET_WAVES;
568569
break;
570+
case KFD_PREEMPT_TYPE_WAVEFRONT_SAVE:
571+
type = SAVE_WAVES;
572+
break;
569573
default:
570574
type = DRAIN_PIPE;
571575
break;
@@ -878,6 +882,32 @@ void kgd_gfx_v9_get_cu_occupancy(struct kgd_dev *kgd, int pasid,
878882
adev->gfx.cu_info.max_waves_per_simd;
879883
}
880884

885+
static void kgd_gfx_v9_program_trap_handler_settings(struct kgd_dev *kgd,
886+
uint32_t vmid, uint64_t tba_addr, uint64_t tma_addr)
887+
{
888+
struct amdgpu_device *adev = get_amdgpu_device(kgd);
889+
890+
lock_srbm(kgd, 0, 0, 0, vmid);
891+
892+
/*
893+
* Program TBA registers
894+
*/
895+
WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_SHADER_TBA_LO),
896+
lower_32_bits(tba_addr >> 8));
897+
WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_SHADER_TBA_HI),
898+
upper_32_bits(tba_addr >> 8));
899+
900+
/*
901+
* Program TMA registers
902+
*/
903+
WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_SHADER_TMA_LO),
904+
lower_32_bits(tma_addr >> 8));
905+
WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_SHADER_TMA_HI),
906+
upper_32_bits(tma_addr >> 8));
907+
908+
unlock_srbm(kgd);
909+
}
910+
881911
const struct kfd2kgd_calls gfx_v9_kfd2kgd = {
882912
.program_sh_mem_settings = kgd_gfx_v9_program_sh_mem_settings,
883913
.set_pasid_vmid_mapping = kgd_gfx_v9_set_pasid_vmid_mapping,
@@ -899,4 +929,5 @@ const struct kfd2kgd_calls gfx_v9_kfd2kgd = {
899929
kgd_gfx_v9_get_atc_vmid_pasid_mapping_info,
900930
.set_vm_context_page_table_base = kgd_gfx_v9_set_vm_context_page_table_base,
901931
.get_cu_occupancy = kgd_gfx_v9_get_cu_occupancy,
932+
.program_trap_handler_settings = kgd_gfx_v9_program_trap_handler_settings,
902933
};

‎drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1414,7 +1414,7 @@ static void amdgpu_ib_preempt_mark_partial_job(struct amdgpu_ring *ring)
14141414
continue;
14151415
}
14161416
job = to_amdgpu_job(s_job);
1417-
if (preempted && job->fence == fence)
1417+
if (preempted && (&job->hw_fence) == fence)
14181418
/* mark the job as preempted */
14191419
job->preemption_status |= AMDGPU_IB_PREEMPTED;
14201420
}

‎drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

Lines changed: 21 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -2829,12 +2829,11 @@ static void amdgpu_device_delay_enable_gfx_off(struct work_struct *work)
28292829
struct amdgpu_device *adev =
28302830
container_of(work, struct amdgpu_device, gfx.gfx_off_delay_work.work);
28312831

2832-
mutex_lock(&adev->gfx.gfx_off_mutex);
2833-
if (!adev->gfx.gfx_off_state && !adev->gfx.gfx_off_req_count) {
2834-
if (!amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, true))
2835-
adev->gfx.gfx_off_state = true;
2836-
}
2837-
mutex_unlock(&adev->gfx.gfx_off_mutex);
2832+
WARN_ON_ONCE(adev->gfx.gfx_off_state);
2833+
WARN_ON_ONCE(adev->gfx.gfx_off_req_count);
2834+
2835+
if (!amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, true))
2836+
adev->gfx.gfx_off_state = true;
28382837
}
28392838

28402839
/**
@@ -3826,7 +3825,10 @@ void amdgpu_device_fini_hw(struct amdgpu_device *adev)
38263825
{
38273826
dev_info(adev->dev, "amdgpu: finishing device.\n");
38283827
flush_delayed_work(&adev->delayed_init_work);
3829-
ttm_bo_lock_delayed_workqueue(&adev->mman.bdev);
3828+
if (adev->mman.initialized) {
3829+
flush_delayed_work(&adev->mman.bdev.wq);
3830+
ttm_bo_lock_delayed_workqueue(&adev->mman.bdev);
3831+
}
38303832
adev->shutdown = true;
38313833

38323834
/* make sure IB test finished before entering exclusive mode
@@ -4448,7 +4450,7 @@ int amdgpu_device_mode1_reset(struct amdgpu_device *adev)
44484450
int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev,
44494451
struct amdgpu_reset_context *reset_context)
44504452
{
4451-
int i, r = 0;
4453+
int i, j, r = 0;
44524454
struct amdgpu_job *job = NULL;
44534455
bool need_full_reset =
44544456
test_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags);
@@ -4472,6 +4474,17 @@ int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev,
44724474
if (!ring || !ring->sched.thread)
44734475
continue;
44744476

4477+
/*clear job fence from fence drv to avoid force_completion
4478+
*leave NULL and vm flush fence in fence drv */
4479+
for (j = 0; j <= ring->fence_drv.num_fences_mask; j++) {
4480+
struct dma_fence *old, **ptr;
4481+
4482+
ptr = &ring->fence_drv.fences[j];
4483+
old = rcu_dereference_protected(*ptr, 1);
4484+
if (old && test_bit(AMDGPU_FENCE_FLAG_EMBED_IN_JOB_BIT, &old->flags)) {
4485+
RCU_INIT_POINTER(*ptr, NULL);
4486+
}
4487+
}
44754488
/* after all hw jobs are reset, hw fence is meaningless, so force_completion */
44764489
amdgpu_fence_driver_force_completion(ring);
44774490
}

‎drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c

Lines changed: 9 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -299,6 +299,9 @@ int amdgpu_discovery_reg_base_init(struct amdgpu_device *adev)
299299
ip->major, ip->minor,
300300
ip->revision);
301301

302+
if (le16_to_cpu(ip->hw_id) == VCN_HWID)
303+
adev->vcn.num_vcn_inst++;
304+
302305
for (k = 0; k < num_base_address; k++) {
303306
/*
304307
* convert the endianness of base addresses in place,
@@ -385,7 +388,7 @@ void amdgpu_discovery_harvest_ip(struct amdgpu_device *adev)
385388
{
386389
struct binary_header *bhdr;
387390
struct harvest_table *harvest_info;
388-
int i;
391+
int i, vcn_harvest_count = 0;
389392

390393
bhdr = (struct binary_header *)adev->mman.discovery_bin;
391394
harvest_info = (struct harvest_table *)(adev->mman.discovery_bin +
@@ -397,8 +400,7 @@ void amdgpu_discovery_harvest_ip(struct amdgpu_device *adev)
397400

398401
switch (le32_to_cpu(harvest_info->list[i].hw_id)) {
399402
case VCN_HWID:
400-
adev->harvest_ip_mask |= AMD_HARVEST_IP_VCN_MASK;
401-
adev->harvest_ip_mask |= AMD_HARVEST_IP_JPEG_MASK;
403+
vcn_harvest_count++;
402404
break;
403405
case DMU_HWID:
404406
adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK;
@@ -407,6 +409,10 @@ void amdgpu_discovery_harvest_ip(struct amdgpu_device *adev)
407409
break;
408410
}
409411
}
412+
if (vcn_harvest_count == adev->vcn.num_vcn_inst) {
413+
adev->harvest_ip_mask |= AMD_HARVEST_IP_VCN_MASK;
414+
adev->harvest_ip_mask |= AMD_HARVEST_IP_JPEG_MASK;
415+
}
410416
}
411417

412418
int amdgpu_discovery_get_gfx_info(struct amdgpu_device *adev)

‎drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c

Lines changed: 0 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -273,9 +273,6 @@ static int amdgpufb_create(struct drm_fb_helper *helper,
273273
return 0;
274274

275275
out:
276-
if (abo) {
277-
278-
}
279276
if (fb && ret) {
280277
drm_gem_object_put(gobj);
281278
drm_framebuffer_unregister_private(fb);

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