@@ -53,26 +53,6 @@ static u32 pdc_reg_read(int reg, u32 i)
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return readl_relaxed (pdc_base + reg + i * sizeof (u32 ));
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}
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- static int qcom_pdc_gic_get_irqchip_state (struct irq_data * d ,
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- enum irqchip_irq_state which ,
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- bool * state )
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- {
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- if (d -> hwirq == GPIO_NO_WAKE_IRQ )
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- return 0 ;
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-
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- return irq_chip_get_parent_state (d , which , state );
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- }
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-
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- static int qcom_pdc_gic_set_irqchip_state (struct irq_data * d ,
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- enum irqchip_irq_state which ,
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- bool value )
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- {
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- if (d -> hwirq == GPIO_NO_WAKE_IRQ )
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- return 0 ;
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-
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- return irq_chip_set_parent_state (d , which , value );
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- }
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-
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static void pdc_enable_intr (struct irq_data * d , bool on )
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{
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int pin_out = d -> hwirq ;
@@ -91,38 +71,16 @@ static void pdc_enable_intr(struct irq_data *d, bool on)
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static void qcom_pdc_gic_disable (struct irq_data * d )
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{
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- if (d -> hwirq == GPIO_NO_WAKE_IRQ )
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- return ;
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-
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pdc_enable_intr (d , false);
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irq_chip_disable_parent (d );
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}
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static void qcom_pdc_gic_enable (struct irq_data * d )
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{
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- if (d -> hwirq == GPIO_NO_WAKE_IRQ )
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- return ;
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-
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pdc_enable_intr (d , true);
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irq_chip_enable_parent (d );
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}
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- static void qcom_pdc_gic_mask (struct irq_data * d )
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- {
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- if (d -> hwirq == GPIO_NO_WAKE_IRQ )
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- return ;
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-
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- irq_chip_mask_parent (d );
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- }
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-
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- static void qcom_pdc_gic_unmask (struct irq_data * d )
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- {
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- if (d -> hwirq == GPIO_NO_WAKE_IRQ )
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- return ;
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-
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- irq_chip_unmask_parent (d );
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- }
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-
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/*
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* GIC does not handle falling edge or active low. To allow falling edge and
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* active low interrupts to be handled at GIC, PDC has an inverter that inverts
@@ -159,14 +117,10 @@ enum pdc_irq_config_bits {
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*/
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static int qcom_pdc_gic_set_type (struct irq_data * d , unsigned int type )
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{
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- int pin_out = d -> hwirq ;
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enum pdc_irq_config_bits pdc_type ;
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enum pdc_irq_config_bits old_pdc_type ;
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int ret ;
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- if (pin_out == GPIO_NO_WAKE_IRQ )
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- return 0 ;
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-
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switch (type ) {
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case IRQ_TYPE_EDGE_RISING :
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pdc_type = PDC_EDGE_RISING ;
@@ -191,8 +145,8 @@ static int qcom_pdc_gic_set_type(struct irq_data *d, unsigned int type)
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return - EINVAL ;
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}
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- old_pdc_type = pdc_reg_read (IRQ_i_CFG , pin_out );
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- pdc_reg_write (IRQ_i_CFG , pin_out , pdc_type );
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+ old_pdc_type = pdc_reg_read (IRQ_i_CFG , d -> hwirq );
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+ pdc_reg_write (IRQ_i_CFG , d -> hwirq , pdc_type );
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ret = irq_chip_set_type_parent (d , type );
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if (ret )
@@ -216,12 +170,12 @@ static int qcom_pdc_gic_set_type(struct irq_data *d, unsigned int type)
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static struct irq_chip qcom_pdc_gic_chip = {
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.name = "PDC" ,
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.irq_eoi = irq_chip_eoi_parent ,
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- .irq_mask = qcom_pdc_gic_mask ,
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- .irq_unmask = qcom_pdc_gic_unmask ,
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+ .irq_mask = irq_chip_mask_parent ,
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+ .irq_unmask = irq_chip_unmask_parent ,
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.irq_disable = qcom_pdc_gic_disable ,
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.irq_enable = qcom_pdc_gic_enable ,
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- .irq_get_irqchip_state = qcom_pdc_gic_get_irqchip_state ,
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- .irq_set_irqchip_state = qcom_pdc_gic_set_irqchip_state ,
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+ .irq_get_irqchip_state = irq_chip_get_parent_state ,
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+ .irq_set_irqchip_state = irq_chip_set_parent_state ,
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.irq_retrigger = irq_chip_retrigger_hierarchy ,
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.irq_set_type = qcom_pdc_gic_set_type ,
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.flags = IRQCHIP_MASK_ON_SUSPEND |
@@ -282,7 +236,7 @@ static int qcom_pdc_alloc(struct irq_domain *domain, unsigned int virq,
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parent_hwirq = get_parent_hwirq (hwirq );
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if (parent_hwirq == PDC_NO_PARENT_IRQ )
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- return 0 ;
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+ return irq_domain_disconnect_hierarchy ( domain -> parent , virq ) ;
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if (type & IRQ_TYPE_EDGE_BOTH )
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type = IRQ_TYPE_EDGE_RISING ;
@@ -319,17 +273,17 @@ static int qcom_pdc_gpio_alloc(struct irq_domain *domain, unsigned int virq,
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if (ret )
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return ret ;
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+ if (hwirq == GPIO_NO_WAKE_IRQ )
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+ return irq_domain_disconnect_hierarchy (domain , virq );
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+
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ret = irq_domain_set_hwirq_and_chip (domain , virq , hwirq ,
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& qcom_pdc_gic_chip , NULL );
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if (ret )
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return ret ;
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- if (hwirq == GPIO_NO_WAKE_IRQ )
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- return 0 ;
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-
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parent_hwirq = get_parent_hwirq (hwirq );
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if (parent_hwirq == PDC_NO_PARENT_IRQ )
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- return 0 ;
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+ return irq_domain_disconnect_hierarchy ( domain -> parent , virq ) ;
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if (type & IRQ_TYPE_EDGE_BOTH )
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type = IRQ_TYPE_EDGE_RISING ;
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