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Evan Quanalexdeucher
Evan Quan
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alexdeucher
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drm/amdgpu: add missing cleanups for more ASICs on UVD/VCE suspend
This is a supplement for commit below: "drm/amdgpu: add missing cleanups for Polaris12 UVD/VCE on suspend". Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Guchun Chen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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6 files changed

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‎drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c

Lines changed: 24 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -698,6 +698,30 @@ static int uvd_v3_1_hw_fini(void *handle)
698698
{
699699
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
700700

701+
/*
702+
* Proper cleanups before halting the HW engine:
703+
* - cancel the delayed idle work
704+
* - enable powergating
705+
* - enable clockgating
706+
* - disable dpm
707+
*
708+
* TODO: to align with the VCN implementation, move the
709+
* jobs for clockgating/powergating/dpm setting to
710+
* ->set_powergating_state().
711+
*/
712+
cancel_delayed_work_sync(&adev->uvd.idle_work);
713+
714+
if (adev->pm.dpm_enabled) {
715+
amdgpu_dpm_enable_uvd(adev, false);
716+
} else {
717+
amdgpu_asic_set_uvd_clocks(adev, 0, 0);
718+
/* shutdown the UVD block */
719+
amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
720+
AMD_PG_STATE_GATE);
721+
amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
722+
AMD_CG_STATE_GATE);
723+
}
724+
701725
if (RREG32(mmUVD_STATUS) != 0)
702726
uvd_v3_1_stop(adev);
703727

‎drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c

Lines changed: 24 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -212,6 +212,30 @@ static int uvd_v4_2_hw_fini(void *handle)
212212
{
213213
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
214214

215+
/*
216+
* Proper cleanups before halting the HW engine:
217+
* - cancel the delayed idle work
218+
* - enable powergating
219+
* - enable clockgating
220+
* - disable dpm
221+
*
222+
* TODO: to align with the VCN implementation, move the
223+
* jobs for clockgating/powergating/dpm setting to
224+
* ->set_powergating_state().
225+
*/
226+
cancel_delayed_work_sync(&adev->uvd.idle_work);
227+
228+
if (adev->pm.dpm_enabled) {
229+
amdgpu_dpm_enable_uvd(adev, false);
230+
} else {
231+
amdgpu_asic_set_uvd_clocks(adev, 0, 0);
232+
/* shutdown the UVD block */
233+
amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
234+
AMD_PG_STATE_GATE);
235+
amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
236+
AMD_CG_STATE_GATE);
237+
}
238+
215239
if (RREG32(mmUVD_STATUS) != 0)
216240
uvd_v4_2_stop(adev);
217241

‎drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c

Lines changed: 24 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -210,6 +210,30 @@ static int uvd_v5_0_hw_fini(void *handle)
210210
{
211211
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
212212

213+
/*
214+
* Proper cleanups before halting the HW engine:
215+
* - cancel the delayed idle work
216+
* - enable powergating
217+
* - enable clockgating
218+
* - disable dpm
219+
*
220+
* TODO: to align with the VCN implementation, move the
221+
* jobs for clockgating/powergating/dpm setting to
222+
* ->set_powergating_state().
223+
*/
224+
cancel_delayed_work_sync(&adev->uvd.idle_work);
225+
226+
if (adev->pm.dpm_enabled) {
227+
amdgpu_dpm_enable_uvd(adev, false);
228+
} else {
229+
amdgpu_asic_set_uvd_clocks(adev, 0, 0);
230+
/* shutdown the UVD block */
231+
amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
232+
AMD_PG_STATE_GATE);
233+
amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
234+
AMD_CG_STATE_GATE);
235+
}
236+
213237
if (RREG32(mmUVD_STATUS) != 0)
214238
uvd_v5_0_stop(adev);
215239

@@ -224,7 +248,6 @@ static int uvd_v5_0_suspend(void *handle)
224248
r = uvd_v5_0_hw_fini(adev);
225249
if (r)
226250
return r;
227-
uvd_v5_0_set_clockgating_state(adev, AMD_CG_STATE_GATE);
228251

229252
return amdgpu_uvd_suspend(adev);
230253
}

‎drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c

Lines changed: 24 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -606,6 +606,30 @@ static int uvd_v7_0_hw_fini(void *handle)
606606
{
607607
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
608608

609+
/*
610+
* Proper cleanups before halting the HW engine:
611+
* - cancel the delayed idle work
612+
* - enable powergating
613+
* - enable clockgating
614+
* - disable dpm
615+
*
616+
* TODO: to align with the VCN implementation, move the
617+
* jobs for clockgating/powergating/dpm setting to
618+
* ->set_powergating_state().
619+
*/
620+
cancel_delayed_work_sync(&adev->uvd.idle_work);
621+
622+
if (adev->pm.dpm_enabled) {
623+
amdgpu_dpm_enable_uvd(adev, false);
624+
} else {
625+
amdgpu_asic_set_uvd_clocks(adev, 0, 0);
626+
/* shutdown the UVD block */
627+
amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
628+
AMD_PG_STATE_GATE);
629+
amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
630+
AMD_CG_STATE_GATE);
631+
}
632+
609633
if (!amdgpu_sriov_vf(adev))
610634
uvd_v7_0_stop(adev);
611635
else {

‎drivers/gpu/drm/amd/amdgpu/vce_v2_0.c

Lines changed: 25 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -477,6 +477,31 @@ static int vce_v2_0_hw_init(void *handle)
477477

478478
static int vce_v2_0_hw_fini(void *handle)
479479
{
480+
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
481+
482+
/*
483+
* Proper cleanups before halting the HW engine:
484+
* - cancel the delayed idle work
485+
* - enable powergating
486+
* - enable clockgating
487+
* - disable dpm
488+
*
489+
* TODO: to align with the VCN implementation, move the
490+
* jobs for clockgating/powergating/dpm setting to
491+
* ->set_powergating_state().
492+
*/
493+
cancel_delayed_work_sync(&adev->vce.idle_work);
494+
495+
if (adev->pm.dpm_enabled) {
496+
amdgpu_dpm_enable_vce(adev, false);
497+
} else {
498+
amdgpu_asic_set_vce_clocks(adev, 0, 0);
499+
amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
500+
AMD_PG_STATE_GATE);
501+
amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
502+
AMD_CG_STATE_GATE);
503+
}
504+
480505
return 0;
481506
}
482507

‎drivers/gpu/drm/amd/amdgpu/vce_v4_0.c

Lines changed: 23 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -542,6 +542,29 @@ static int vce_v4_0_hw_fini(void *handle)
542542
{
543543
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
544544

545+
/*
546+
* Proper cleanups before halting the HW engine:
547+
* - cancel the delayed idle work
548+
* - enable powergating
549+
* - enable clockgating
550+
* - disable dpm
551+
*
552+
* TODO: to align with the VCN implementation, move the
553+
* jobs for clockgating/powergating/dpm setting to
554+
* ->set_powergating_state().
555+
*/
556+
cancel_delayed_work_sync(&adev->vce.idle_work);
557+
558+
if (adev->pm.dpm_enabled) {
559+
amdgpu_dpm_enable_vce(adev, false);
560+
} else {
561+
amdgpu_asic_set_vce_clocks(adev, 0, 0);
562+
amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
563+
AMD_PG_STATE_GATE);
564+
amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
565+
AMD_CG_STATE_GATE);
566+
}
567+
545568
if (!amdgpu_sriov_vf(adev)) {
546569
/* vce_v4_0_wait_for_idle(handle); */
547570
vce_v4_0_stop(adev);

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