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Merge tag 'drm-fixes-2021-08-20-3' of git://anongit.freedesktop.org/drm/drm
Pull drm fixes from Dave Airlie: "Regularly scheduled fixes. The ttm one solves a problem of GPU drivers failing to load if debugfs is off in Kconfig, otherwise the i915 and mediatek, and amdgpu fixes all fairly normal. Nouveau has a couple of display fixes, but it has a fix for a longstanding race condition in it's memory manager code, and the fix mostly removes some code that wasn't working properly and has no userspace users. This fix makes the diffstat kinda larger but in a good (negative line-count) way. core: - fix drm_wait_vblank uapi copying bug ttm: - fix debugfs init when debugfs is off amdgpu: - vega10 SMU workload fix - DCN VM fix - DCN 3.01 watermark fix amdkfd: - SVM fix nouveau: - ampere display fixes - remove MM misfeature to fix a longstanding race condition i915: - tweaked display workaround for all PCHs - eDP MSO pipe sanity for ADL-P fix - remove unused symbol export mediatek: - AAL output size setting - Delete component in remove function" * tag 'drm-fixes-2021-08-20-3' of git://anongit.freedesktop.org/drm/drm: drm/amd/display: Use DCN30 watermark calc for DCN301 drm/i915/dp: remove superfluous EXPORT_SYMBOL() drm/i915/edp: fix eDP MSO pipe sanity checks for ADL-P drm/i915: Tweaked Wa_14010685332 for all PCHs drm/nouveau: rip out nvkm_client.super drm/nouveau: block a bunch of classes from userspace drm/nouveau/fifo/nv50-: rip out dma channels drm/nouveau/kms/nv50: workaround EFI GOP window channel format differences drm/nouveau/disp: power down unused DP links during init drm/nouveau: recognise GA107 drm: Copy drm_wait_vblank to user before returning drm/amd/display: Ensure DCN save after VM setup drm/amdkfd: fix random KFDSVMRangeTest.SetGetAttributesTest test failure drm/amd/pm: change the workload type for some cards Revert "drm/amd/pm: fix workload mismatch on vega10" drm: ttm: Don't bail from ttm_global_init if debugfs_create_dir fails drm/mediatek: Add component_del in OVL and COLOR remove function drm/mediatek: Add AAL output size configuration
2 parents 3db903a + daa7772 commit 8ba9fbe

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61 files changed

+224
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lines changed

‎drivers/gpu/drm/amd/amdkfd/kfd_svm.c

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3026,6 +3026,14 @@ svm_range_get_attr(struct kfd_process *p, uint64_t start, uint64_t size,
30263026
pr_debug("svms 0x%p [0x%llx 0x%llx] nattr 0x%x\n", &p->svms, start,
30273027
start + size - 1, nattr);
30283028

3029+
/* Flush pending deferred work to avoid racing with deferred actions from
3030+
* previous memory map changes (e.g. munmap). Concurrent memory map changes
3031+
* can still race with get_attr because we don't hold the mmap lock. But that
3032+
* would be a race condition in the application anyway, and undefined
3033+
* behaviour is acceptable in that case.
3034+
*/
3035+
flush_work(&p->svms.deferred_list_work);
3036+
30293037
mmap_read_lock(mm);
30303038
if (!svm_range_is_valid(mm, start, size)) {
30313039
pr_debug("invalid range\n");

‎drivers/gpu/drm/amd/display/dc/core/dc.c

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1530,6 +1530,12 @@ void dc_z10_restore(struct dc *dc)
15301530
if (dc->hwss.z10_restore)
15311531
dc->hwss.z10_restore(dc);
15321532
}
1533+
1534+
void dc_z10_save_init(struct dc *dc)
1535+
{
1536+
if (dc->hwss.z10_save_init)
1537+
dc->hwss.z10_save_init(dc);
1538+
}
15331539
#endif
15341540
/*
15351541
* Applies given context to HW and copy it into current context.

‎drivers/gpu/drm/amd/display/dc/core/dc_vm_helper.c

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -47,6 +47,9 @@ int dc_setup_system_context(struct dc *dc, struct dc_phy_addr_space_config *pa_c
4747
*/
4848
memcpy(&dc->vm_pa_config, pa_config, sizeof(struct dc_phy_addr_space_config));
4949
dc->vm_pa_config.valid = true;
50+
#if defined(CONFIG_DRM_AMD_DC_DCN)
51+
dc_z10_save_init(dc);
52+
#endif
5053
}
5154

5255
return num_vmids;

‎drivers/gpu/drm/amd/display/dc/dc.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1338,6 +1338,7 @@ void dc_hardware_release(struct dc *dc);
13381338
bool dc_set_psr_allow_active(struct dc *dc, bool enable);
13391339
#if defined(CONFIG_DRM_AMD_DC_DCN)
13401340
void dc_z10_restore(struct dc *dc);
1341+
void dc_z10_save_init(struct dc *dc);
13411342
#endif
13421343

13431344
bool dc_enable_dmub_notifications(struct dc *dc);

‎drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c

Lines changed: 1 addition & 95 deletions
Original file line numberDiff line numberDiff line change
@@ -1622,106 +1622,12 @@ static void dcn301_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *b
16221622
dml_init_instance(&dc->dml, &dcn3_01_soc, &dcn3_01_ip, DML_PROJECT_DCN30);
16231623
}
16241624

1625-
static void calculate_wm_set_for_vlevel(
1626-
int vlevel,
1627-
struct wm_range_table_entry *table_entry,
1628-
struct dcn_watermarks *wm_set,
1629-
struct display_mode_lib *dml,
1630-
display_e2e_pipe_params_st *pipes,
1631-
int pipe_cnt)
1632-
{
1633-
double dram_clock_change_latency_cached = dml->soc.dram_clock_change_latency_us;
1634-
1635-
ASSERT(vlevel < dml->soc.num_states);
1636-
/* only pipe 0 is read for voltage and dcf/soc clocks */
1637-
pipes[0].clks_cfg.voltage = vlevel;
1638-
pipes[0].clks_cfg.dcfclk_mhz = dml->soc.clock_limits[vlevel].dcfclk_mhz;
1639-
pipes[0].clks_cfg.socclk_mhz = dml->soc.clock_limits[vlevel].socclk_mhz;
1640-
1641-
dml->soc.dram_clock_change_latency_us = table_entry->pstate_latency_us;
1642-
dml->soc.sr_exit_time_us = table_entry->sr_exit_time_us;
1643-
dml->soc.sr_enter_plus_exit_time_us = table_entry->sr_enter_plus_exit_time_us;
1644-
1645-
wm_set->urgent_ns = get_wm_urgent(dml, pipes, pipe_cnt) * 1000;
1646-
wm_set->cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(dml, pipes, pipe_cnt) * 1000;
1647-
wm_set->cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(dml, pipes, pipe_cnt) * 1000;
1648-
wm_set->cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(dml, pipes, pipe_cnt) * 1000;
1649-
wm_set->pte_meta_urgent_ns = get_wm_memory_trip(dml, pipes, pipe_cnt) * 1000;
1650-
wm_set->frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(dml, pipes, pipe_cnt) * 1000;
1651-
wm_set->frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(dml, pipes, pipe_cnt) * 1000;
1652-
wm_set->urgent_latency_ns = get_urgent_latency(dml, pipes, pipe_cnt) * 1000;
1653-
dml->soc.dram_clock_change_latency_us = dram_clock_change_latency_cached;
1654-
1655-
}
1656-
1657-
static void dcn301_calculate_wm_and_dlg(
1658-
struct dc *dc, struct dc_state *context,
1659-
display_e2e_pipe_params_st *pipes,
1660-
int pipe_cnt,
1661-
int vlevel_req)
1662-
{
1663-
int i, pipe_idx;
1664-
int vlevel, vlevel_max;
1665-
struct wm_range_table_entry *table_entry;
1666-
struct clk_bw_params *bw_params = dc->clk_mgr->bw_params;
1667-
1668-
ASSERT(bw_params);
1669-
1670-
vlevel_max = bw_params->clk_table.num_entries - 1;
1671-
1672-
/* WM Set D */
1673-
table_entry = &bw_params->wm_table.entries[WM_D];
1674-
if (table_entry->wm_type == WM_TYPE_RETRAINING)
1675-
vlevel = 0;
1676-
else
1677-
vlevel = vlevel_max;
1678-
calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.d,
1679-
&context->bw_ctx.dml, pipes, pipe_cnt);
1680-
/* WM Set C */
1681-
table_entry = &bw_params->wm_table.entries[WM_C];
1682-
vlevel = min(max(vlevel_req, 2), vlevel_max);
1683-
calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.c,
1684-
&context->bw_ctx.dml, pipes, pipe_cnt);
1685-
/* WM Set B */
1686-
table_entry = &bw_params->wm_table.entries[WM_B];
1687-
vlevel = min(max(vlevel_req, 1), vlevel_max);
1688-
calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.b,
1689-
&context->bw_ctx.dml, pipes, pipe_cnt);
1690-
1691-
/* WM Set A */
1692-
table_entry = &bw_params->wm_table.entries[WM_A];
1693-
vlevel = min(vlevel_req, vlevel_max);
1694-
calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.a,
1695-
&context->bw_ctx.dml, pipes, pipe_cnt);
1696-
1697-
for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
1698-
if (!context->res_ctx.pipe_ctx[i].stream)
1699-
continue;
1700-
1701-
pipes[pipe_idx].clks_cfg.dispclk_mhz = get_dispclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt);
1702-
pipes[pipe_idx].clks_cfg.dppclk_mhz = get_dppclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
1703-
1704-
if (dc->config.forced_clocks) {
1705-
pipes[pipe_idx].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz;
1706-
pipes[pipe_idx].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz;
1707-
}
1708-
if (dc->debug.min_disp_clk_khz > pipes[pipe_idx].clks_cfg.dispclk_mhz * 1000)
1709-
pipes[pipe_idx].clks_cfg.dispclk_mhz = dc->debug.min_disp_clk_khz / 1000.0;
1710-
if (dc->debug.min_dpp_clk_khz > pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000)
1711-
pipes[pipe_idx].clks_cfg.dppclk_mhz = dc->debug.min_dpp_clk_khz / 1000.0;
1712-
1713-
pipe_idx++;
1714-
}
1715-
1716-
dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel);
1717-
}
1718-
17191625
static struct resource_funcs dcn301_res_pool_funcs = {
17201626
.destroy = dcn301_destroy_resource_pool,
17211627
.link_enc_create = dcn301_link_encoder_create,
17221628
.panel_cntl_create = dcn301_panel_cntl_create,
17231629
.validate_bandwidth = dcn30_validate_bandwidth,
1724-
.calculate_wm_and_dlg = dcn301_calculate_wm_and_dlg,
1630+
.calculate_wm_and_dlg = dcn30_calculate_wm_and_dlg,
17251631
.update_soc_for_wm_a = dcn30_update_soc_for_wm_a,
17261632
.populate_dml_pipes = dcn30_populate_dml_pipes_from_context,
17271633
.acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer,

‎drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c

Lines changed: 12 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -404,6 +404,18 @@ void dcn31_update_info_frame(struct pipe_ctx *pipe_ctx)
404404
&pipe_ctx->stream_res.encoder_info_frame);
405405
}
406406
}
407+
void dcn31_z10_save_init(struct dc *dc)
408+
{
409+
union dmub_rb_cmd cmd;
410+
411+
memset(&cmd, 0, sizeof(cmd));
412+
cmd.dcn_restore.header.type = DMUB_CMD__IDLE_OPT;
413+
cmd.dcn_restore.header.sub_type = DMUB_CMD__IDLE_OPT_DCN_SAVE_INIT;
414+
415+
dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd);
416+
dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv);
417+
dc_dmub_srv_wait_idle(dc->ctx->dmub_srv);
418+
}
407419

408420
void dcn31_z10_restore(struct dc *dc)
409421
{

‎drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -44,6 +44,7 @@ void dcn31_enable_power_gating_plane(
4444
void dcn31_update_info_frame(struct pipe_ctx *pipe_ctx);
4545

4646
void dcn31_z10_restore(struct dc *dc);
47+
void dcn31_z10_save_init(struct dc *dc);
4748

4849
void dcn31_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool power_on);
4950
int dcn31_init_sys_ctx(struct dce_hwseq *hws, struct dc *dc, struct dc_phy_addr_space_config *pa_config);

‎drivers/gpu/drm/amd/display/dc/dcn31/dcn31_init.c

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -97,6 +97,7 @@ static const struct hw_sequencer_funcs dcn31_funcs = {
9797
.set_abm_immediate_disable = dcn21_set_abm_immediate_disable,
9898
.set_pipe = dcn21_set_pipe,
9999
.z10_restore = dcn31_z10_restore,
100+
.z10_save_init = dcn31_z10_save_init,
100101
.is_abm_supported = dcn31_is_abm_supported,
101102
.set_disp_pattern_generator = dcn30_set_disp_pattern_generator,
102103
.update_visual_confirm_color = dcn20_update_visual_confirm_color,

‎drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -237,6 +237,7 @@ struct hw_sequencer_funcs {
237237
int width, int height, int offset);
238238

239239
void (*z10_restore)(struct dc *dc);
240+
void (*z10_save_init)(struct dc *dc);
240241

241242
void (*update_visual_confirm_color)(struct dc *dc,
242243
struct pipe_ctx *pipe_ctx,

‎drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -856,6 +856,11 @@ enum dmub_cmd_idle_opt_type {
856856
* DCN hardware restore.
857857
*/
858858
DMUB_CMD__IDLE_OPT_DCN_RESTORE = 0,
859+
860+
/**
861+
* DCN hardware save.
862+
*/
863+
DMUB_CMD__IDLE_OPT_DCN_SAVE_INIT = 1
859864
};
860865

861866
/**

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