Skip to content

Commit 8e5f17e

Browse files
bebarinobebarino
committed
Merge tag 'clk-imx-5.14' of git://git.kernel.org/pub/scm/linux/kernel/git/abelvesa/linux into clk-imx
Pull i.MX clk driver updates from Abel Vesa: - Remove audio ipg clock from i.MX8MP - Fix naming typo of clock compatible string - Remove deprecated legacy clock binding for SCU clock driver - Use common clk-imx8qxp for both i.MX8QXP and i.MX8QM - Add multiple clocks to clk-imx8qxp driver (enet, hdmi, lcdif, audio, parallel interface) - Add dedicated clock ops for paralel interface - Different fixes for clocks controlled by ATF - Fix different issues related to parallel interface clocks - Add A53/A72 frequency scaling support clk-scu driver - Add special case for DCSS clock on suspend for clk-scu driver - Add parent save/restore on suspend/resume to clk-scu driver - Skip runtime PM enablement for CPU clocks in clk-scu driver - Remove the sys1_pll/sys2_pll clock gates for i.MX8MQ and their bindings * tag 'clk-imx-5.14' of git://git.kernel.org/pub/scm/linux/kernel/git/abelvesa/linux: clk: imx8mq: remove SYS PLL 1/2 clock gates clk: imx: scu: Do not enable runtime PM for CPU clks clk: imx: scu: add parent save and restore clk: imx: scu: Only save DC SS clock using non-cached clock rate clk: imx: scu: Add A72 frequency scaling support clk: imx: scu: Add A53 frequency scaling support clk: imx: scu: bypass pi_pll enable status restore clk: imx: scu: detach pd if can't power up clk: imx: scu: bypass cpu clock save and restore clk: imx: scu: add parallel port clock ops clk: imx: scu: add more scu clocks clk: imx: scu: add enet rgmii gpr clocks clk: imx8qm: add clock valid resource checking clk: imx8qxp: add clock valid checking mechnism clk: imx: scu: add gpr clocks support clk: imx: scu: remove legacy scu clock binding support dt-bindings: arm: imx: scu: drop deprecated legacy clock binding dt-bindings: arm: imx: scu: fix naming typo of clk compatible string clk: imx: Remove the audio ipg clock from imx8mp
2 parents 6efb943 + c586f53 commit 8e5f17e

File tree

11 files changed

+814
-353
lines changed

11 files changed

+814
-353
lines changed

‎Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt

Lines changed: 4 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -86,13 +86,11 @@ This binding uses the common clock binding[1].
8686

8787
Required properties:
8888
- compatible: Should be one of:
89-
"fsl,imx8qm-clock"
90-
"fsl,imx8qxp-clock"
89+
"fsl,imx8qm-clk"
90+
"fsl,imx8qxp-clk"
9191
followed by "fsl,scu-clk"
92-
- #clock-cells: Should be either
93-
2: Contains the Resource and Clock ID value.
94-
or
95-
1: Contains the Clock ID value. (DEPRECATED)
92+
- #clock-cells: Should be 2.
93+
Contains the Resource and Clock ID value.
9694
- clocks: List of clock specifiers, must contain an entry for
9795
each required entry in clock-names
9896
- clock-names: Should include entries "xtal_32KHz", "xtal_24MHz"

‎drivers/clk/imx/Makefile

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -27,7 +27,8 @@ obj-$(CONFIG_CLK_IMX8MP) += clk-imx8mp.o
2727
obj-$(CONFIG_CLK_IMX8MQ) += clk-imx8mq.o
2828

2929
obj-$(CONFIG_MXC_CLK_SCU) += clk-imx-scu.o clk-imx-lpcg-scu.o
30-
clk-imx-scu-$(CONFIG_CLK_IMX8QXP) += clk-scu.o clk-imx8qxp.o
30+
clk-imx-scu-$(CONFIG_CLK_IMX8QXP) += clk-scu.o clk-imx8qxp.o \
31+
clk-imx8qxp-rsrc.o clk-imx8qm-rsrc.o
3132
clk-imx-lpcg-scu-$(CONFIG_CLK_IMX8QXP) += clk-lpcg-scu.o clk-imx8qxp-lpcg.o
3233

3334
obj-$(CONFIG_CLK_IMX1) += clk-imx1.o

‎drivers/clk/imx/clk-imx8mp.c

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -556,7 +556,6 @@ static int imx8mp_clocks_probe(struct platform_device *pdev)
556556
hws[IMX8MP_CLK_MIPI_DSI_ESC_RX] = imx8m_clk_hw_composite_bus("mipi_dsi_esc_rx", imx8mp_mipi_dsi_esc_rx_sels, ccm_base + 0x9200);
557557

558558
hws[IMX8MP_CLK_IPG_ROOT] = imx_clk_hw_divider2("ipg_root", "ahb_root", ccm_base + 0x9080, 0, 1);
559-
hws[IMX8MP_CLK_IPG_AUDIO_ROOT] = imx_clk_hw_divider2("ipg_audio_root", "audio_ahb", ccm_base + 0x9180, 0, 1);
560559

561560
hws[IMX8MP_CLK_DRAM_ALT] = imx8m_clk_hw_composite("dram_alt", imx8mp_dram_alt_sels, ccm_base + 0xa000);
562561
hws[IMX8MP_CLK_DRAM_APB] = imx8m_clk_hw_composite_critical("dram_apb", imx8mp_dram_apb_sels, ccm_base + 0xa080);

‎drivers/clk/imx/clk-imx8mq.c

Lines changed: 18 additions & 38 deletions
Original file line numberDiff line numberDiff line change
@@ -358,46 +358,26 @@ static int imx8mq_clocks_probe(struct platform_device *pdev)
358358
hws[IMX8MQ_VIDEO2_PLL_OUT] = imx_clk_hw_sscg_pll("video2_pll_out", video2_pll_out_sels, ARRAY_SIZE(video2_pll_out_sels), 0, 0, 0, base + 0x54, 0);
359359

360360
/* SYS PLL1 fixed output */
361-
hws[IMX8MQ_SYS1_PLL_40M_CG] = imx_clk_hw_gate("sys1_pll_40m_cg", "sys1_pll_out", base + 0x30, 9);
362-
hws[IMX8MQ_SYS1_PLL_80M_CG] = imx_clk_hw_gate("sys1_pll_80m_cg", "sys1_pll_out", base + 0x30, 11);
363-
hws[IMX8MQ_SYS1_PLL_100M_CG] = imx_clk_hw_gate("sys1_pll_100m_cg", "sys1_pll_out", base + 0x30, 13);
364-
hws[IMX8MQ_SYS1_PLL_133M_CG] = imx_clk_hw_gate("sys1_pll_133m_cg", "sys1_pll_out", base + 0x30, 15);
365-
hws[IMX8MQ_SYS1_PLL_160M_CG] = imx_clk_hw_gate("sys1_pll_160m_cg", "sys1_pll_out", base + 0x30, 17);
366-
hws[IMX8MQ_SYS1_PLL_200M_CG] = imx_clk_hw_gate("sys1_pll_200m_cg", "sys1_pll_out", base + 0x30, 19);
367-
hws[IMX8MQ_SYS1_PLL_266M_CG] = imx_clk_hw_gate("sys1_pll_266m_cg", "sys1_pll_out", base + 0x30, 21);
368-
hws[IMX8MQ_SYS1_PLL_400M_CG] = imx_clk_hw_gate("sys1_pll_400m_cg", "sys1_pll_out", base + 0x30, 23);
369-
hws[IMX8MQ_SYS1_PLL_800M_CG] = imx_clk_hw_gate("sys1_pll_800m_cg", "sys1_pll_out", base + 0x30, 25);
370-
371-
hws[IMX8MQ_SYS1_PLL_40M] = imx_clk_hw_fixed_factor("sys1_pll_40m", "sys1_pll_40m_cg", 1, 20);
372-
hws[IMX8MQ_SYS1_PLL_80M] = imx_clk_hw_fixed_factor("sys1_pll_80m", "sys1_pll_80m_cg", 1, 10);
373-
hws[IMX8MQ_SYS1_PLL_100M] = imx_clk_hw_fixed_factor("sys1_pll_100m", "sys1_pll_100m_cg", 1, 8);
374-
hws[IMX8MQ_SYS1_PLL_133M] = imx_clk_hw_fixed_factor("sys1_pll_133m", "sys1_pll_133m_cg", 1, 6);
375-
hws[IMX8MQ_SYS1_PLL_160M] = imx_clk_hw_fixed_factor("sys1_pll_160m", "sys1_pll_160m_cg", 1, 5);
376-
hws[IMX8MQ_SYS1_PLL_200M] = imx_clk_hw_fixed_factor("sys1_pll_200m", "sys1_pll_200m_cg", 1, 4);
377-
hws[IMX8MQ_SYS1_PLL_266M] = imx_clk_hw_fixed_factor("sys1_pll_266m", "sys1_pll_266m_cg", 1, 3);
378-
hws[IMX8MQ_SYS1_PLL_400M] = imx_clk_hw_fixed_factor("sys1_pll_400m", "sys1_pll_400m_cg", 1, 2);
379-
hws[IMX8MQ_SYS1_PLL_800M] = imx_clk_hw_fixed_factor("sys1_pll_800m", "sys1_pll_800m_cg", 1, 1);
361+
hws[IMX8MQ_SYS1_PLL_40M] = imx_clk_hw_fixed_factor("sys1_pll_40m", "sys1_pll_out", 1, 20);
362+
hws[IMX8MQ_SYS1_PLL_80M] = imx_clk_hw_fixed_factor("sys1_pll_80m", "sys1_pll_out", 1, 10);
363+
hws[IMX8MQ_SYS1_PLL_100M] = imx_clk_hw_fixed_factor("sys1_pll_100m", "sys1_pll_out", 1, 8);
364+
hws[IMX8MQ_SYS1_PLL_133M] = imx_clk_hw_fixed_factor("sys1_pll_133m", "sys1_pll_out", 1, 6);
365+
hws[IMX8MQ_SYS1_PLL_160M] = imx_clk_hw_fixed_factor("sys1_pll_160m", "sys1_pll_out", 1, 5);
366+
hws[IMX8MQ_SYS1_PLL_200M] = imx_clk_hw_fixed_factor("sys1_pll_200m", "sys1_pll_out", 1, 4);
367+
hws[IMX8MQ_SYS1_PLL_266M] = imx_clk_hw_fixed_factor("sys1_pll_266m", "sys1_pll_out", 1, 3);
368+
hws[IMX8MQ_SYS1_PLL_400M] = imx_clk_hw_fixed_factor("sys1_pll_400m", "sys1_pll_out", 1, 2);
369+
hws[IMX8MQ_SYS1_PLL_800M] = imx_clk_hw_fixed_factor("sys1_pll_800m", "sys1_pll_out", 1, 1);
380370

381371
/* SYS PLL2 fixed output */
382-
hws[IMX8MQ_SYS2_PLL_50M_CG] = imx_clk_hw_gate("sys2_pll_50m_cg", "sys2_pll_out", base + 0x3c, 9);
383-
hws[IMX8MQ_SYS2_PLL_100M_CG] = imx_clk_hw_gate("sys2_pll_100m_cg", "sys2_pll_out", base + 0x3c, 11);
384-
hws[IMX8MQ_SYS2_PLL_125M_CG] = imx_clk_hw_gate("sys2_pll_125m_cg", "sys2_pll_out", base + 0x3c, 13);
385-
hws[IMX8MQ_SYS2_PLL_166M_CG] = imx_clk_hw_gate("sys2_pll_166m_cg", "sys2_pll_out", base + 0x3c, 15);
386-
hws[IMX8MQ_SYS2_PLL_200M_CG] = imx_clk_hw_gate("sys2_pll_200m_cg", "sys2_pll_out", base + 0x3c, 17);
387-
hws[IMX8MQ_SYS2_PLL_250M_CG] = imx_clk_hw_gate("sys2_pll_250m_cg", "sys2_pll_out", base + 0x3c, 19);
388-
hws[IMX8MQ_SYS2_PLL_333M_CG] = imx_clk_hw_gate("sys2_pll_333m_cg", "sys2_pll_out", base + 0x3c, 21);
389-
hws[IMX8MQ_SYS2_PLL_500M_CG] = imx_clk_hw_gate("sys2_pll_500m_cg", "sys2_pll_out", base + 0x3c, 23);
390-
hws[IMX8MQ_SYS2_PLL_1000M_CG] = imx_clk_hw_gate("sys2_pll_1000m_cg", "sys2_pll_out", base + 0x3c, 25);
391-
392-
hws[IMX8MQ_SYS2_PLL_50M] = imx_clk_hw_fixed_factor("sys2_pll_50m", "sys2_pll_50m_cg", 1, 20);
393-
hws[IMX8MQ_SYS2_PLL_100M] = imx_clk_hw_fixed_factor("sys2_pll_100m", "sys2_pll_100m_cg", 1, 10);
394-
hws[IMX8MQ_SYS2_PLL_125M] = imx_clk_hw_fixed_factor("sys2_pll_125m", "sys2_pll_125m_cg", 1, 8);
395-
hws[IMX8MQ_SYS2_PLL_166M] = imx_clk_hw_fixed_factor("sys2_pll_166m", "sys2_pll_166m_cg", 1, 6);
396-
hws[IMX8MQ_SYS2_PLL_200M] = imx_clk_hw_fixed_factor("sys2_pll_200m", "sys2_pll_200m_cg", 1, 5);
397-
hws[IMX8MQ_SYS2_PLL_250M] = imx_clk_hw_fixed_factor("sys2_pll_250m", "sys2_pll_250m_cg", 1, 4);
398-
hws[IMX8MQ_SYS2_PLL_333M] = imx_clk_hw_fixed_factor("sys2_pll_333m", "sys2_pll_333m_cg", 1, 3);
399-
hws[IMX8MQ_SYS2_PLL_500M] = imx_clk_hw_fixed_factor("sys2_pll_500m", "sys2_pll_500m_cg", 1, 2);
400-
hws[IMX8MQ_SYS2_PLL_1000M] = imx_clk_hw_fixed_factor("sys2_pll_1000m", "sys2_pll_1000m_cg", 1, 1);
372+
hws[IMX8MQ_SYS2_PLL_50M] = imx_clk_hw_fixed_factor("sys2_pll_50m", "sys2_pll_out", 1, 20);
373+
hws[IMX8MQ_SYS2_PLL_100M] = imx_clk_hw_fixed_factor("sys2_pll_100m", "sys2_pll_out", 1, 10);
374+
hws[IMX8MQ_SYS2_PLL_125M] = imx_clk_hw_fixed_factor("sys2_pll_125m", "sys2_pll_out", 1, 8);
375+
hws[IMX8MQ_SYS2_PLL_166M] = imx_clk_hw_fixed_factor("sys2_pll_166m", "sys2_pll_out", 1, 6);
376+
hws[IMX8MQ_SYS2_PLL_200M] = imx_clk_hw_fixed_factor("sys2_pll_200m", "sys2_pll_out", 1, 5);
377+
hws[IMX8MQ_SYS2_PLL_250M] = imx_clk_hw_fixed_factor("sys2_pll_250m", "sys2_pll_out", 1, 4);
378+
hws[IMX8MQ_SYS2_PLL_333M] = imx_clk_hw_fixed_factor("sys2_pll_333m", "sys2_pll_out", 1, 3);
379+
hws[IMX8MQ_SYS2_PLL_500M] = imx_clk_hw_fixed_factor("sys2_pll_500m", "sys2_pll_out", 1, 2);
380+
hws[IMX8MQ_SYS2_PLL_1000M] = imx_clk_hw_fixed_factor("sys2_pll_1000m", "sys2_pll_out", 1, 1);
401381

402382
hws[IMX8MQ_CLK_MON_AUDIO_PLL1_DIV] = imx_clk_hw_divider("audio_pll1_out_monitor", "audio_pll1_bypass", base + 0x78, 0, 3);
403383
hws[IMX8MQ_CLK_MON_AUDIO_PLL2_DIV] = imx_clk_hw_divider("audio_pll2_out_monitor", "audio_pll2_bypass", base + 0x78, 4, 3);

‎drivers/clk/imx/clk-imx8qm-rsrc.c

Lines changed: 116 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,116 @@
1+
// SPDX-License-Identifier: GPL-2.0+
2+
/*
3+
* Copyright 2019-2021 NXP
4+
* Dong Aisheng <[email protected]>
5+
*/
6+
7+
#include <dt-bindings/firmware/imx/rsrc.h>
8+
9+
#include "clk-scu.h"
10+
11+
/* Keep sorted in the ascending order */
12+
static const u32 imx8qm_clk_scu_rsrc_table[] = {
13+
IMX_SC_R_A53,
14+
IMX_SC_R_A72,
15+
IMX_SC_R_DC_0_VIDEO0,
16+
IMX_SC_R_DC_0_VIDEO1,
17+
IMX_SC_R_DC_0,
18+
IMX_SC_R_DC_0_PLL_0,
19+
IMX_SC_R_DC_0_PLL_1,
20+
IMX_SC_R_DC_1_VIDEO0,
21+
IMX_SC_R_DC_1_VIDEO1,
22+
IMX_SC_R_DC_1,
23+
IMX_SC_R_DC_1_PLL_0,
24+
IMX_SC_R_DC_1_PLL_1,
25+
IMX_SC_R_SPI_0,
26+
IMX_SC_R_SPI_1,
27+
IMX_SC_R_SPI_2,
28+
IMX_SC_R_SPI_3,
29+
IMX_SC_R_UART_0,
30+
IMX_SC_R_UART_1,
31+
IMX_SC_R_UART_2,
32+
IMX_SC_R_UART_3,
33+
IMX_SC_R_UART_4,
34+
IMX_SC_R_EMVSIM_0,
35+
IMX_SC_R_EMVSIM_1,
36+
IMX_SC_R_I2C_0,
37+
IMX_SC_R_I2C_1,
38+
IMX_SC_R_I2C_2,
39+
IMX_SC_R_I2C_3,
40+
IMX_SC_R_I2C_4,
41+
IMX_SC_R_ADC_0,
42+
IMX_SC_R_ADC_1,
43+
IMX_SC_R_FTM_0,
44+
IMX_SC_R_FTM_1,
45+
IMX_SC_R_CAN_0,
46+
IMX_SC_R_GPU_0_PID0,
47+
IMX_SC_R_GPU_1_PID0,
48+
IMX_SC_R_PWM_0,
49+
IMX_SC_R_PWM_1,
50+
IMX_SC_R_PWM_2,
51+
IMX_SC_R_PWM_3,
52+
IMX_SC_R_PWM_4,
53+
IMX_SC_R_PWM_5,
54+
IMX_SC_R_PWM_6,
55+
IMX_SC_R_PWM_7,
56+
IMX_SC_R_GPT_0,
57+
IMX_SC_R_GPT_1,
58+
IMX_SC_R_GPT_2,
59+
IMX_SC_R_GPT_3,
60+
IMX_SC_R_GPT_4,
61+
IMX_SC_R_FSPI_0,
62+
IMX_SC_R_FSPI_1,
63+
IMX_SC_R_SDHC_0,
64+
IMX_SC_R_SDHC_1,
65+
IMX_SC_R_SDHC_2,
66+
IMX_SC_R_ENET_0,
67+
IMX_SC_R_ENET_1,
68+
IMX_SC_R_MLB_0,
69+
IMX_SC_R_USB_2,
70+
IMX_SC_R_NAND,
71+
IMX_SC_R_LVDS_0,
72+
IMX_SC_R_LVDS_0_PWM_0,
73+
IMX_SC_R_LVDS_0_I2C_0,
74+
IMX_SC_R_LVDS_0_I2C_1,
75+
IMX_SC_R_LVDS_1,
76+
IMX_SC_R_LVDS_1_PWM_0,
77+
IMX_SC_R_LVDS_1_I2C_0,
78+
IMX_SC_R_LVDS_1_I2C_1,
79+
IMX_SC_R_M4_0_I2C,
80+
IMX_SC_R_M4_1_I2C,
81+
IMX_SC_R_AUDIO_PLL_0,
82+
IMX_SC_R_VPU_UART,
83+
IMX_SC_R_VPUCORE,
84+
IMX_SC_R_MIPI_0,
85+
IMX_SC_R_MIPI_0_PWM_0,
86+
IMX_SC_R_MIPI_0_I2C_0,
87+
IMX_SC_R_MIPI_0_I2C_1,
88+
IMX_SC_R_MIPI_1,
89+
IMX_SC_R_MIPI_1_PWM_0,
90+
IMX_SC_R_MIPI_1_I2C_0,
91+
IMX_SC_R_MIPI_1_I2C_1,
92+
IMX_SC_R_CSI_0,
93+
IMX_SC_R_CSI_0_PWM_0,
94+
IMX_SC_R_CSI_0_I2C_0,
95+
IMX_SC_R_CSI_1,
96+
IMX_SC_R_CSI_1_PWM_0,
97+
IMX_SC_R_CSI_1_I2C_0,
98+
IMX_SC_R_HDMI,
99+
IMX_SC_R_HDMI_I2S,
100+
IMX_SC_R_HDMI_I2C_0,
101+
IMX_SC_R_HDMI_PLL_0,
102+
IMX_SC_R_HDMI_RX,
103+
IMX_SC_R_HDMI_RX_BYPASS,
104+
IMX_SC_R_HDMI_RX_I2C_0,
105+
IMX_SC_R_AUDIO_PLL_1,
106+
IMX_SC_R_AUDIO_CLK_0,
107+
IMX_SC_R_AUDIO_CLK_1,
108+
IMX_SC_R_HDMI_RX_PWM_0,
109+
IMX_SC_R_HDMI_PLL_1,
110+
IMX_SC_R_VPU,
111+
};
112+
113+
const struct imx_clk_scu_rsrc_table imx_clk_scu_rsrc_imx8qm = {
114+
.rsrc = imx8qm_clk_scu_rsrc_table,
115+
.num = ARRAY_SIZE(imx8qm_clk_scu_rsrc_table),
116+
};

‎drivers/clk/imx/clk-imx8qxp-rsrc.c

Lines changed: 89 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,89 @@
1+
// SPDX-License-Identifier: GPL-2.0+
2+
/*
3+
* Copyright 2019-2021 NXP
4+
* Dong Aisheng <[email protected]>
5+
*/
6+
7+
#include <dt-bindings/firmware/imx/rsrc.h>
8+
9+
#include "clk-scu.h"
10+
11+
/* Keep sorted in the ascending order */
12+
static const u32 imx8qxp_clk_scu_rsrc_table[] = {
13+
IMX_SC_R_DC_0_VIDEO0,
14+
IMX_SC_R_DC_0_VIDEO1,
15+
IMX_SC_R_DC_0,
16+
IMX_SC_R_DC_0_PLL_0,
17+
IMX_SC_R_DC_0_PLL_1,
18+
IMX_SC_R_SPI_0,
19+
IMX_SC_R_SPI_1,
20+
IMX_SC_R_SPI_2,
21+
IMX_SC_R_SPI_3,
22+
IMX_SC_R_UART_0,
23+
IMX_SC_R_UART_1,
24+
IMX_SC_R_UART_2,
25+
IMX_SC_R_UART_3,
26+
IMX_SC_R_I2C_0,
27+
IMX_SC_R_I2C_1,
28+
IMX_SC_R_I2C_2,
29+
IMX_SC_R_I2C_3,
30+
IMX_SC_R_ADC_0,
31+
IMX_SC_R_FTM_0,
32+
IMX_SC_R_FTM_1,
33+
IMX_SC_R_CAN_0,
34+
IMX_SC_R_GPU_0_PID0,
35+
IMX_SC_R_LCD_0,
36+
IMX_SC_R_LCD_0_PWM_0,
37+
IMX_SC_R_PWM_0,
38+
IMX_SC_R_PWM_1,
39+
IMX_SC_R_PWM_2,
40+
IMX_SC_R_PWM_3,
41+
IMX_SC_R_PWM_4,
42+
IMX_SC_R_PWM_5,
43+
IMX_SC_R_PWM_6,
44+
IMX_SC_R_PWM_7,
45+
IMX_SC_R_GPT_0,
46+
IMX_SC_R_GPT_1,
47+
IMX_SC_R_GPT_2,
48+
IMX_SC_R_GPT_3,
49+
IMX_SC_R_GPT_4,
50+
IMX_SC_R_FSPI_0,
51+
IMX_SC_R_FSPI_1,
52+
IMX_SC_R_SDHC_0,
53+
IMX_SC_R_SDHC_1,
54+
IMX_SC_R_SDHC_2,
55+
IMX_SC_R_ENET_0,
56+
IMX_SC_R_ENET_1,
57+
IMX_SC_R_MLB_0,
58+
IMX_SC_R_USB_2,
59+
IMX_SC_R_NAND,
60+
IMX_SC_R_LVDS_0,
61+
IMX_SC_R_LVDS_1,
62+
IMX_SC_R_M4_0_I2C,
63+
IMX_SC_R_ELCDIF_PLL,
64+
IMX_SC_R_AUDIO_PLL_0,
65+
IMX_SC_R_PI_0,
66+
IMX_SC_R_PI_0_PLL,
67+
IMX_SC_R_MIPI_0,
68+
IMX_SC_R_MIPI_0_PWM_0,
69+
IMX_SC_R_MIPI_0_I2C_0,
70+
IMX_SC_R_MIPI_0_I2C_1,
71+
IMX_SC_R_MIPI_1,
72+
IMX_SC_R_MIPI_1_PWM_0,
73+
IMX_SC_R_MIPI_1_I2C_0,
74+
IMX_SC_R_MIPI_1_I2C_1,
75+
IMX_SC_R_CSI_0,
76+
IMX_SC_R_CSI_0_PWM_0,
77+
IMX_SC_R_CSI_0_I2C_0,
78+
IMX_SC_R_AUDIO_PLL_1,
79+
IMX_SC_R_AUDIO_CLK_0,
80+
IMX_SC_R_AUDIO_CLK_1,
81+
IMX_SC_R_A35,
82+
IMX_SC_R_VPU_DEC_0,
83+
IMX_SC_R_VPU_ENC_0,
84+
};
85+
86+
const struct imx_clk_scu_rsrc_table imx_clk_scu_rsrc_imx8qxp = {
87+
.rsrc = imx8qxp_clk_scu_rsrc_table,
88+
.num = ARRAY_SIZE(imx8qxp_clk_scu_rsrc_table),
89+
};

0 commit comments

Comments
 (0)