Skip to content

Commit 904ec4b

Browse files
geertugeertu
committed
pinctrl: renesas: r8a779{51,6,65}: Reduce non-functional differences
Change whitespace in the pin control drivers for R-Car H3 ES2.0+, R-Car M3-W/M3-W+, and R-Car M3-N, to reduce the differences among these very similar drivers. These changes have no functional impact. Signed-off-by: Geert Uytterhoeven <[email protected]> Reviewed-by: Niklas Söderlund <[email protected]> Link: https://lore.kernel.org/r/527b45ebfc664a80e41cb0136677db7260e11437.1619785375.git.geert+renesas@glider.be
1 parent cf04bbe commit 904ec4b

File tree

3 files changed

+46
-44
lines changed

3 files changed

+46
-44
lines changed

‎drivers/pinctrl/renesas/pfc-r8a77951.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -241,7 +241,7 @@
241241
#define GPSR6_3 F_(SSI_SDATA1_A, IP15_3_0)
242242
#define GPSR6_2 F_(SSI_SDATA0, IP14_31_28)
243243
#define GPSR6_1 F_(SSI_WS01239, IP14_27_24)
244-
#define GPSR6_0 F_(SSI_SCK01239, IP14_23_20)
244+
#define GPSR6_0 F_(SSI_SCK01239, IP14_23_20)
245245

246246
/* GPSR7 */
247247
#define GPSR7_3 FM(GP7_03)
@@ -668,7 +668,7 @@ static const u16 pinmux_data[] = {
668668
PINMUX_IPSR_PHYS_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, I2C_SEL_5_0, SEL_ETHERAVB_0),
669669
PINMUX_IPSR_PHYS_MSEL(IP0_23_20, MSIOF2_TXD_C, I2C_SEL_5_0, SEL_MSIOF2_2),
670670
PINMUX_IPSR_PHYS_MSEL(IP0_23_20, RTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0),
671-
PINMUX_IPSR_PHYS(IP0_23_20, SDA5, I2C_SEL_5_1),
671+
PINMUX_IPSR_PHYS(IP0_23_20, SDA5, I2C_SEL_5_1),
672672

673673
PINMUX_IPSR_GPSR(IP0_27_24, IRQ0),
674674
PINMUX_IPSR_GPSR(IP0_27_24, QPOLB),

‎drivers/pinctrl/renesas/pfc-r8a7796.c

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1549,7 +1549,7 @@ static const u16 pinmux_data[] = {
15491549
* core will do the right thing and skip trying to mux the pin
15501550
* while still applying configuration to it.
15511551
*/
1552-
#define FM(x) PINMUX_DATA(x##_MARK, 0),
1552+
#define FM(x) PINMUX_DATA(x##_MARK, 0),
15531553
PINMUX_STATIC
15541554
#undef FM
15551555
};
@@ -4234,7 +4234,7 @@ static const struct {
42344234
SH_PFC_PIN_GROUP(avb_link),
42354235
SH_PFC_PIN_GROUP(avb_magic),
42364236
SH_PFC_PIN_GROUP(avb_phy_int),
4237-
SH_PFC_PIN_GROUP_ALIAS(avb_mdc, avb_mdio), /* Deprecated */
4237+
SH_PFC_PIN_GROUP_ALIAS(avb_mdc, avb_mdio), /* Deprecated */
42384238
SH_PFC_PIN_GROUP(avb_mdio),
42394239
SH_PFC_PIN_GROUP(avb_mii),
42404240
SH_PFC_PIN_GROUP(avb_avtp_pps),
@@ -5991,7 +5991,8 @@ static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
59915991
{ /* sentinel */ },
59925992
};
59935993

5994-
static int r8a7796_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
5994+
static int r8a7796_pin_to_pocctrl(struct sh_pfc *pfc,
5995+
unsigned int pin, u32 *pocctrl)
59955996
{
59965997
int bit = -EINVAL;
59975998

‎drivers/pinctrl/renesas/pfc-r8a77965.c

Lines changed: 40 additions & 39 deletions
Original file line numberDiff line numberDiff line change
@@ -666,14 +666,14 @@ static const u16 pinmux_data[] = {
666666
PINMUX_IPSR_MSEL(IP0_15_12, TX4_A, SEL_SCIF4_0),
667667
PINMUX_IPSR_GPSR(IP0_19_16, FSCLKST2_N_A),
668668

669-
PINMUX_IPSR_PHYS_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, I2C_SEL_5_0, SEL_ETHERAVB_0),
670-
PINMUX_IPSR_PHYS_MSEL(IP0_19_16, MSIOF2_RXD_C, I2C_SEL_5_0, SEL_MSIOF2_2),
671-
PINMUX_IPSR_PHYS_MSEL(IP0_19_16, CTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0),
669+
PINMUX_IPSR_PHYS_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, I2C_SEL_5_0, SEL_ETHERAVB_0),
670+
PINMUX_IPSR_PHYS_MSEL(IP0_19_16, MSIOF2_RXD_C, I2C_SEL_5_0, SEL_MSIOF2_2),
671+
PINMUX_IPSR_PHYS_MSEL(IP0_19_16, CTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0),
672672
PINMUX_IPSR_PHYS(IP0_19_16, SCL5, I2C_SEL_5_1),
673673

674-
PINMUX_IPSR_PHYS_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, I2C_SEL_5_0, SEL_ETHERAVB_0),
675-
PINMUX_IPSR_PHYS_MSEL(IP0_23_20, MSIOF2_TXD_C, I2C_SEL_5_0, SEL_MSIOF2_2),
676-
PINMUX_IPSR_PHYS_MSEL(IP0_23_20, RTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0),
674+
PINMUX_IPSR_PHYS_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, I2C_SEL_5_0, SEL_ETHERAVB_0),
675+
PINMUX_IPSR_PHYS_MSEL(IP0_23_20, MSIOF2_TXD_C, I2C_SEL_5_0, SEL_MSIOF2_2),
676+
PINMUX_IPSR_PHYS_MSEL(IP0_23_20, RTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0),
677677
PINMUX_IPSR_PHYS(IP0_23_20, SDA5, I2C_SEL_5_1),
678678

679679
PINMUX_IPSR_GPSR(IP0_27_24, IRQ0),
@@ -727,16 +727,16 @@ static const u16 pinmux_data[] = {
727727
PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA6_B, SEL_VIN4_1),
728728
PINMUX_IPSR_MSEL(IP1_19_16, IECLK_B, SEL_IEBUS_1),
729729

730-
PINMUX_IPSR_PHYS_MSEL(IP1_23_20, PWM1_A, I2C_SEL_3_0, SEL_PWM1_0),
731-
PINMUX_IPSR_PHYS_MSEL(IP1_23_20, HRX3_D, I2C_SEL_3_0, SEL_HSCIF3_3),
732-
PINMUX_IPSR_PHYS_MSEL(IP1_23_20, VI4_DATA7_B, I2C_SEL_3_0, SEL_VIN4_1),
733-
PINMUX_IPSR_PHYS_MSEL(IP1_23_20, IERX_B, I2C_SEL_3_0, SEL_IEBUS_1),
734-
PINMUX_IPSR_PHYS(IP1_23_20, SCL3, I2C_SEL_3_1),
730+
PINMUX_IPSR_PHYS_MSEL(IP1_23_20, PWM1_A, I2C_SEL_3_0, SEL_PWM1_0),
731+
PINMUX_IPSR_PHYS_MSEL(IP1_23_20, HRX3_D, I2C_SEL_3_0, SEL_HSCIF3_3),
732+
PINMUX_IPSR_PHYS_MSEL(IP1_23_20, VI4_DATA7_B, I2C_SEL_3_0, SEL_VIN4_1),
733+
PINMUX_IPSR_PHYS_MSEL(IP1_23_20, IERX_B, I2C_SEL_3_0, SEL_IEBUS_1),
734+
PINMUX_IPSR_PHYS(IP1_23_20, SCL3, I2C_SEL_3_1),
735735

736-
PINMUX_IPSR_PHYS_MSEL(IP1_27_24, PWM2_A, I2C_SEL_3_0, SEL_PWM2_0),
737-
PINMUX_IPSR_PHYS_MSEL(IP1_27_24, HTX3_D, I2C_SEL_3_0, SEL_HSCIF3_3),
738-
PINMUX_IPSR_PHYS_MSEL(IP1_27_24, IETX_B, I2C_SEL_3_0, SEL_IEBUS_1),
739-
PINMUX_IPSR_PHYS(IP1_27_24, SDA3, I2C_SEL_3_1),
736+
PINMUX_IPSR_PHYS_MSEL(IP1_27_24, PWM2_A, I2C_SEL_3_0, SEL_PWM2_0),
737+
PINMUX_IPSR_PHYS_MSEL(IP1_27_24, HTX3_D, I2C_SEL_3_0, SEL_HSCIF3_3),
738+
PINMUX_IPSR_PHYS_MSEL(IP1_27_24, IETX_B, I2C_SEL_3_0, SEL_IEBUS_1),
739+
PINMUX_IPSR_PHYS(IP1_27_24, SDA3, I2C_SEL_3_1),
740740

741741
PINMUX_IPSR_GPSR(IP1_31_28, A0),
742742
PINMUX_IPSR_GPSR(IP1_31_28, LCDOUT16),
@@ -1171,13 +1171,13 @@ static const u16 pinmux_data[] = {
11711171
PINMUX_IPSR_MSEL(IP11_15_12, SDA2_B, SEL_I2C2_1),
11721172

11731173
PINMUX_IPSR_MSEL(IP11_19_16, SD1_CD, I2C_SEL_0_0),
1174-
PINMUX_IPSR_PHYS_MSEL(IP11_19_16, NFRB_N_A, I2C_SEL_0_0, SEL_NDF_0),
1175-
PINMUX_IPSR_PHYS_MSEL(IP11_19_16, SIM0_CLK_B, I2C_SEL_0_0, SEL_SIMCARD_1),
1174+
PINMUX_IPSR_PHYS_MSEL(IP11_19_16, NFRB_N_A, I2C_SEL_0_0, SEL_NDF_0),
1175+
PINMUX_IPSR_PHYS_MSEL(IP11_19_16, SIM0_CLK_B, I2C_SEL_0_0, SEL_SIMCARD_1),
11761176
PINMUX_IPSR_PHYS(IP11_19_16, SCL0, I2C_SEL_0_1),
11771177

11781178
PINMUX_IPSR_MSEL(IP11_23_20, SD1_WP, I2C_SEL_0_0),
1179-
PINMUX_IPSR_PHYS_MSEL(IP11_23_20, NFCE_N_A, I2C_SEL_0_0, SEL_NDF_0),
1180-
PINMUX_IPSR_PHYS_MSEL(IP11_23_20, SIM0_D_B, I2C_SEL_0_0, SEL_SIMCARD_1),
1179+
PINMUX_IPSR_PHYS_MSEL(IP11_23_20, NFCE_N_A, I2C_SEL_0_0, SEL_NDF_0),
1180+
PINMUX_IPSR_PHYS_MSEL(IP11_23_20, SIM0_D_B, I2C_SEL_0_0, SEL_SIMCARD_1),
11811181
PINMUX_IPSR_PHYS(IP11_23_20, SDA0, I2C_SEL_0_1),
11821182

11831183
PINMUX_IPSR_GPSR(IP11_27_24, SCK0),
@@ -1553,7 +1553,7 @@ static const u16 pinmux_data[] = {
15531553
* core will do the right thing and skip trying to mux the pin
15541554
* while still applying configuration to it.
15551555
*/
1556-
#define FM(x) PINMUX_DATA(x##_MARK, 0),
1556+
#define FM(x) PINMUX_DATA(x##_MARK, 0),
15571557
PINMUX_STATIC
15581558
#undef FM
15591559
};
@@ -4224,24 +4224,24 @@ static const unsigned int vin4_data18_a_pins[] = {
42244224
RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
42254225
RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
42264226
RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
4227-
RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
4228-
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4229-
RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4230-
RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4231-
RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4232-
RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4227+
RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
4228+
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4229+
RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4230+
RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4231+
RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4232+
RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
42334233
};
42344234

42354235
static const unsigned int vin4_data18_a_mux[] = {
42364236
VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
42374237
VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
42384238
VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
4239-
VI4_DATA10_MARK, VI4_DATA11_MARK,
4240-
VI4_DATA12_MARK, VI4_DATA13_MARK,
4241-
VI4_DATA14_MARK, VI4_DATA15_MARK,
4242-
VI4_DATA18_MARK, VI4_DATA19_MARK,
4243-
VI4_DATA20_MARK, VI4_DATA21_MARK,
4244-
VI4_DATA22_MARK, VI4_DATA23_MARK,
4239+
VI4_DATA10_MARK, VI4_DATA11_MARK,
4240+
VI4_DATA12_MARK, VI4_DATA13_MARK,
4241+
VI4_DATA14_MARK, VI4_DATA15_MARK,
4242+
VI4_DATA18_MARK, VI4_DATA19_MARK,
4243+
VI4_DATA20_MARK, VI4_DATA21_MARK,
4244+
VI4_DATA22_MARK, VI4_DATA23_MARK,
42454245
};
42464246

42474247
static const union vin_data vin4_data_a_pins = {
@@ -4294,12 +4294,12 @@ static const unsigned int vin4_data18_b_mux[] = {
42944294
VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
42954295
VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
42964296
VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
4297-
VI4_DATA10_MARK, VI4_DATA11_MARK,
4298-
VI4_DATA12_MARK, VI4_DATA13_MARK,
4299-
VI4_DATA14_MARK, VI4_DATA15_MARK,
4300-
VI4_DATA18_MARK, VI4_DATA19_MARK,
4301-
VI4_DATA20_MARK, VI4_DATA21_MARK,
4302-
VI4_DATA22_MARK, VI4_DATA23_MARK,
4297+
VI4_DATA10_MARK, VI4_DATA11_MARK,
4298+
VI4_DATA12_MARK, VI4_DATA13_MARK,
4299+
VI4_DATA14_MARK, VI4_DATA15_MARK,
4300+
VI4_DATA18_MARK, VI4_DATA19_MARK,
4301+
VI4_DATA20_MARK, VI4_DATA21_MARK,
4302+
VI4_DATA22_MARK, VI4_DATA23_MARK,
43034303
};
43044304

43054305
static const union vin_data vin4_data_b_pins = {
@@ -6248,7 +6248,8 @@ static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
62486248
{ /* sentinel */ },
62496249
};
62506250

6251-
static int r8a77965_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
6251+
static int r8a77965_pin_to_pocctrl(struct sh_pfc *pfc,
6252+
unsigned int pin, u32 *pocctrl)
62526253
{
62536254
int bit = -EINVAL;
62546255

0 commit comments

Comments
 (0)