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Alain Volmatbebarino
Alain Volmat
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bebarino
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clk: st: clkgen-pll: embed soc clock outputs within compatible data
In order to avoid relying on the old style description via the DT clock-output-names, add compatible data describing the flexgen outputs clocks for all STiH407/STiH410 and STiH418 SOCs. In order to ease transition between the two methods, this commit introduce the new compatible without removing the old method. Once DTs will be fixed, the method relying on DT clock-output-names will be removed from this driver as well as old compatibles. Signed-off-by: Alain Volmat <[email protected]> Reviewed-by: Patrice Chotard <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
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‎drivers/clk/st/clkgen-pll.c

Lines changed: 106 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -57,6 +57,17 @@ struct clkgen_pll_data {
5757
const struct clk_ops *ops;
5858
};
5959

60+
struct clkgen_clk_out {
61+
const char *name;
62+
unsigned long flags;
63+
};
64+
65+
struct clkgen_pll_data_clks {
66+
struct clkgen_pll_data *data;
67+
const struct clkgen_clk_out *outputs;
68+
};
69+
70+
6071
static const struct clk_ops stm_pll3200c32_ops;
6172
static const struct clk_ops stm_pll3200c32_a9_ops;
6273
static const struct clk_ops stm_pll4600c28_ops;
@@ -74,6 +85,28 @@ static const struct clkgen_pll_data st_pll3200c32_cx_0 = {
7485
.ops = &stm_pll3200c32_ops,
7586
};
7687

88+
static const struct clkgen_pll_data_clks st_pll3200c32_cx_0_legacy_data = {
89+
.data = (struct clkgen_pll_data *)&st_pll3200c32_cx_0,
90+
};
91+
92+
static const struct clkgen_clk_out st_pll3200c32_ax_0_clks[] = {
93+
{ .name = "clk-s-a0-pll-odf-0", },
94+
};
95+
96+
static const struct clkgen_pll_data_clks st_pll3200c32_a0_data = {
97+
.data = (struct clkgen_pll_data *)&st_pll3200c32_cx_0,
98+
.outputs = st_pll3200c32_ax_0_clks,
99+
};
100+
101+
static const struct clkgen_clk_out st_pll3200c32_cx_0_clks[] = {
102+
{ .name = "clk-s-c0-pll0-odf-0", },
103+
};
104+
105+
static const struct clkgen_pll_data_clks st_pll3200c32_c0_data = {
106+
.data = (struct clkgen_pll_data *)&st_pll3200c32_cx_0,
107+
.outputs = st_pll3200c32_cx_0_clks,
108+
};
109+
77110
static const struct clkgen_pll_data st_pll3200c32_cx_1 = {
78111
/* 407 C0 PLL1 */
79112
.pdn_status = CLKGEN_FIELD(0x2c8, 0x1, 8),
@@ -87,6 +120,19 @@ static const struct clkgen_pll_data st_pll3200c32_cx_1 = {
87120
.ops = &stm_pll3200c32_ops,
88121
};
89122

123+
static const struct clkgen_pll_data_clks st_pll3200c32_cx_1_legacy_data = {
124+
.data = (struct clkgen_pll_data *)&st_pll3200c32_cx_1,
125+
};
126+
127+
static const struct clkgen_clk_out st_pll3200c32_cx_1_clks[] = {
128+
{ .name = "clk-s-c0-pll1-odf-0", },
129+
};
130+
131+
static const struct clkgen_pll_data_clks st_pll3200c32_c1_data = {
132+
.data = (struct clkgen_pll_data *)&st_pll3200c32_cx_1,
133+
.outputs = st_pll3200c32_cx_1_clks,
134+
};
135+
90136
static const struct clkgen_pll_data st_pll3200c32_407_a9 = {
91137
/* 407 A9 */
92138
.pdn_status = CLKGEN_FIELD(0x1a8, 0x1, 0),
@@ -104,6 +150,15 @@ static const struct clkgen_pll_data st_pll3200c32_407_a9 = {
104150
.ops = &stm_pll3200c32_a9_ops,
105151
};
106152

153+
static const struct clkgen_clk_out st_pll3200c32_407_a9_clks[] = {
154+
{ .name = "clockgen-a9-pll-odf", },
155+
};
156+
157+
static const struct clkgen_pll_data_clks st_pll3200c32_407_a9_data = {
158+
.data = (struct clkgen_pll_data *)&st_pll3200c32_407_a9,
159+
.outputs = st_pll3200c32_407_a9_clks,
160+
};
161+
107162
static struct clkgen_pll_data st_pll4600c28_418_a9 = {
108163
/* 418 A9 */
109164
.pdn_status = CLKGEN_FIELD(0x1a8, 0x1, 0),
@@ -120,6 +175,15 @@ static struct clkgen_pll_data st_pll4600c28_418_a9 = {
120175
.ops = &stm_pll4600c28_ops,
121176
};
122177

178+
static const struct clkgen_clk_out st_pll4600c28_418_a9_clks[] = {
179+
{ .name = "clockgen-a9-pll-odf", },
180+
};
181+
182+
static const struct clkgen_pll_data_clks st_pll4600c28_418_a9_data = {
183+
.data = (struct clkgen_pll_data *)&st_pll4600c28_418_a9,
184+
.outputs = st_pll4600c28_418_a9_clks,
185+
};
186+
123187
/**
124188
* DOC: Clock Generated by PLL, rate set and enabled by bootloader
125189
*
@@ -684,7 +748,7 @@ static struct clk * __init clkgen_odf_register(const char *parent_name,
684748

685749

686750
static void __init clkgen_c32_pll_setup(struct device_node *np,
687-
struct clkgen_pll_data *data)
751+
struct clkgen_pll_data_clks *datac)
688752
{
689753
struct clk *clk;
690754
const char *parent_name, *pll_name;
@@ -704,14 +768,14 @@ static void __init clkgen_c32_pll_setup(struct device_node *np,
704768

705769
of_clk_detect_critical(np, 0, &pll_flags);
706770

707-
clk = clkgen_pll_register(parent_name, data, pll_base, pll_flags,
708-
np->name, data->lock);
771+
clk = clkgen_pll_register(parent_name, datac->data, pll_base, pll_flags,
772+
np->name, datac->data->lock);
709773
if (IS_ERR(clk))
710774
return;
711775

712776
pll_name = __clk_get_name(clk);
713777

714-
num_odfs = data->num_odfs;
778+
num_odfs = datac->data->num_odfs;
715779

716780
clk_data = kzalloc(sizeof(*clk_data), GFP_KERNEL);
717781
if (!clk_data)
@@ -729,14 +793,21 @@ static void __init clkgen_c32_pll_setup(struct device_node *np,
729793
const char *clk_name;
730794
unsigned long odf_flags = 0;
731795

732-
if (of_property_read_string_index(np, "clock-output-names",
733-
odf, &clk_name))
734-
return;
796+
if (datac->outputs) {
797+
clk_name = datac->outputs[odf].name;
798+
odf_flags = datac->outputs[odf].flags;
799+
} else {
800+
if (of_property_read_string_index(np,
801+
"clock-output-names",
802+
odf, &clk_name))
803+
return;
735804

736-
of_clk_detect_critical(np, odf, &odf_flags);
805+
of_clk_detect_critical(np, odf, &odf_flags);
806+
}
737807

738-
clk = clkgen_odf_register(pll_name, pll_base, data, odf_flags,
739-
odf, &clkgena_c32_odf_lock, clk_name);
808+
clk = clkgen_odf_register(pll_name, pll_base, datac->data,
809+
odf_flags, odf, &clkgena_c32_odf_lock,
810+
clk_name);
740811
if (IS_ERR(clk))
741812
goto err;
742813

@@ -754,27 +825,48 @@ static void __init clkgen_c32_pll_setup(struct device_node *np,
754825
static void __init clkgen_c32_pll0_setup(struct device_node *np)
755826
{
756827
clkgen_c32_pll_setup(np,
757-
(struct clkgen_pll_data *) &st_pll3200c32_cx_0);
828+
(struct clkgen_pll_data_clks *) &st_pll3200c32_cx_0_legacy_data);
758829
}
759830
CLK_OF_DECLARE(c32_pll0, "st,clkgen-pll0", clkgen_c32_pll0_setup);
760831

832+
static void __init clkgen_c32_pll0_a0_setup(struct device_node *np)
833+
{
834+
clkgen_c32_pll_setup(np,
835+
(struct clkgen_pll_data_clks *) &st_pll3200c32_a0_data);
836+
}
837+
CLK_OF_DECLARE(c32_pll0_a0, "st,clkgen-pll0-a0", clkgen_c32_pll0_a0_setup);
838+
839+
static void __init clkgen_c32_pll0_c0_setup(struct device_node *np)
840+
{
841+
clkgen_c32_pll_setup(np,
842+
(struct clkgen_pll_data_clks *) &st_pll3200c32_c0_data);
843+
}
844+
CLK_OF_DECLARE(c32_pll0_c0, "st,clkgen-pll0-c0", clkgen_c32_pll0_c0_setup);
845+
761846
static void __init clkgen_c32_pll1_setup(struct device_node *np)
762847
{
763848
clkgen_c32_pll_setup(np,
764-
(struct clkgen_pll_data *) &st_pll3200c32_cx_1);
849+
(struct clkgen_pll_data_clks *) &st_pll3200c32_cx_1_legacy_data);
765850
}
766851
CLK_OF_DECLARE(c32_pll1, "st,clkgen-pll1", clkgen_c32_pll1_setup);
767852

853+
static void __init clkgen_c32_pll1_c0_setup(struct device_node *np)
854+
{
855+
clkgen_c32_pll_setup(np,
856+
(struct clkgen_pll_data_clks *) &st_pll3200c32_c1_data);
857+
}
858+
CLK_OF_DECLARE(c32_pll1_c0, "st,clkgen-pll1-c0", clkgen_c32_pll1_c0_setup);
859+
768860
static void __init clkgen_c32_plla9_setup(struct device_node *np)
769861
{
770862
clkgen_c32_pll_setup(np,
771-
(struct clkgen_pll_data *) &st_pll3200c32_407_a9);
863+
(struct clkgen_pll_data_clks *) &st_pll3200c32_407_a9_data);
772864
}
773865
CLK_OF_DECLARE(c32_plla9, "st,stih407-clkgen-plla9", clkgen_c32_plla9_setup);
774866

775867
static void __init clkgen_c28_plla9_setup(struct device_node *np)
776868
{
777869
clkgen_c32_pll_setup(np,
778-
(struct clkgen_pll_data *) &st_pll4600c28_418_a9);
870+
(struct clkgen_pll_data_clks *) &st_pll4600c28_418_a9_data);
779871
}
780872
CLK_OF_DECLARE(c28_plla9, "st,stih418-clkgen-plla9", clkgen_c28_plla9_setup);

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