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948 | 948 | <&bpmp TEGRA194_CLK_XUSB_SS>,
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949 | 949 | <&bpmp TEGRA194_CLK_XUSB_FS>;
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950 | 950 | clock-names = "dev", "ss", "ss_src", "fs_src";
|
| 951 | + interconnects = <&mc TEGRA194_MEMORY_CLIENT_XUSB_DEVR &emc>, |
| 952 | + <&mc TEGRA194_MEMORY_CLIENT_XUSB_DEVW &emc>; |
| 953 | + interconnect-names = "dma-mem", "write"; |
| 954 | + iommus = <&smmu TEGRA194_SID_XUSB_DEV>; |
951 | 955 | power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBB>,
|
952 | 956 | <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>;
|
953 | 957 | power-domain-names = "dev", "ss";
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|
977 | 981 | "xusb_ss", "xusb_ss_src", "xusb_hs_src",
|
978 | 982 | "xusb_fs_src", "pll_u_480m", "clk_m",
|
979 | 983 | "pll_e";
|
| 984 | + interconnects = <&mc TEGRA194_MEMORY_CLIENT_XUSB_HOSTR &emc>, |
| 985 | + <&mc TEGRA194_MEMORY_CLIENT_XUSB_HOSTW &emc>; |
| 986 | + interconnect-names = "dma-mem", "write"; |
| 987 | + iommus = <&smmu TEGRA194_SID_XUSB_HOST>; |
980 | 988 |
|
981 | 989 | power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBC>,
|
982 | 990 | <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>;
|
|
2469 | 2477 | * for 8x and 11.025x sample rate streams.
|
2470 | 2478 | */
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2471 | 2479 | assigned-clock-rates = <258000000>;
|
| 2480 | + |
| 2481 | + interconnects = <&mc TEGRA194_MEMORY_CLIENT_APEDMAR &emc>, |
| 2482 | + <&mc TEGRA194_MEMORY_CLIENT_APEDMAW &emc>; |
| 2483 | + interconnect-names = "dma-mem", "write"; |
| 2484 | + iommus = <&smmu TEGRA194_SID_APE>; |
2472 | 2485 | };
|
2473 | 2486 |
|
2474 | 2487 | tcu: tcu {
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