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Elaine Zhangmmind
Elaine Zhang
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clk: rockchip: support more core div setting
Use arrays to support more core independent div settings. A55 supports each core to work at different frequencies, and each core has an independent divider control. Signed-off-by: Elaine Zhang <[email protected]> Reviewed-by: Kever Yang <[email protected]> Acked-by: Stephen Boyd <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Heiko Stuebner <[email protected]>
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13 files changed

+98
-77
lines changed

13 files changed

+98
-77
lines changed

‎drivers/clk/rockchip/clk-cpu.c

Lines changed: 29 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -84,10 +84,10 @@ static unsigned long rockchip_cpuclk_recalc_rate(struct clk_hw *hw,
8484
{
8585
struct rockchip_cpuclk *cpuclk = to_rockchip_cpuclk_hw(hw);
8686
const struct rockchip_cpuclk_reg_data *reg_data = cpuclk->reg_data;
87-
u32 clksel0 = readl_relaxed(cpuclk->reg_base + reg_data->core_reg);
87+
u32 clksel0 = readl_relaxed(cpuclk->reg_base + reg_data->core_reg[0]);
8888

89-
clksel0 >>= reg_data->div_core_shift;
90-
clksel0 &= reg_data->div_core_mask;
89+
clksel0 >>= reg_data->div_core_shift[0];
90+
clksel0 &= reg_data->div_core_mask[0];
9191
return parent_rate / (clksel0 + 1);
9292
}
9393

@@ -120,6 +120,7 @@ static int rockchip_cpuclk_pre_rate_change(struct rockchip_cpuclk *cpuclk,
120120
const struct rockchip_cpuclk_rate_table *rate;
121121
unsigned long alt_prate, alt_div;
122122
unsigned long flags;
123+
int i = 0;
123124

124125
/* check validity of the new rate */
125126
rate = rockchip_get_cpuclk_settings(cpuclk, ndata->new_rate);
@@ -142,10 +143,10 @@ static int rockchip_cpuclk_pre_rate_change(struct rockchip_cpuclk *cpuclk,
142143
if (alt_prate > ndata->old_rate) {
143144
/* calculate dividers */
144145
alt_div = DIV_ROUND_UP(alt_prate, ndata->old_rate) - 1;
145-
if (alt_div > reg_data->div_core_mask) {
146+
if (alt_div > reg_data->div_core_mask[0]) {
146147
pr_warn("%s: limiting alt-divider %lu to %d\n",
147-
__func__, alt_div, reg_data->div_core_mask);
148-
alt_div = reg_data->div_core_mask;
148+
__func__, alt_div, reg_data->div_core_mask[0]);
149+
alt_div = reg_data->div_core_mask[0];
149150
}
150151

151152
/*
@@ -158,19 +159,17 @@ static int rockchip_cpuclk_pre_rate_change(struct rockchip_cpuclk *cpuclk,
158159
pr_debug("%s: setting div %lu as alt-rate %lu > old-rate %lu\n",
159160
__func__, alt_div, alt_prate, ndata->old_rate);
160161

161-
writel(HIWORD_UPDATE(alt_div, reg_data->div_core_mask,
162-
reg_data->div_core_shift) |
163-
HIWORD_UPDATE(reg_data->mux_core_alt,
164-
reg_data->mux_core_mask,
165-
reg_data->mux_core_shift),
166-
cpuclk->reg_base + reg_data->core_reg);
167-
} else {
168-
/* select alternate parent */
169-
writel(HIWORD_UPDATE(reg_data->mux_core_alt,
170-
reg_data->mux_core_mask,
171-
reg_data->mux_core_shift),
172-
cpuclk->reg_base + reg_data->core_reg);
162+
for (i = 0; i < reg_data->num_cores; i++) {
163+
writel(HIWORD_UPDATE(alt_div, reg_data->div_core_mask[i],
164+
reg_data->div_core_shift[i]),
165+
cpuclk->reg_base + reg_data->core_reg[i]);
166+
}
173167
}
168+
/* select alternate parent */
169+
writel(HIWORD_UPDATE(reg_data->mux_core_alt,
170+
reg_data->mux_core_mask,
171+
reg_data->mux_core_shift),
172+
cpuclk->reg_base + reg_data->core_reg[0]);
174173

175174
spin_unlock_irqrestore(cpuclk->lock, flags);
176175
return 0;
@@ -182,6 +181,7 @@ static int rockchip_cpuclk_post_rate_change(struct rockchip_cpuclk *cpuclk,
182181
const struct rockchip_cpuclk_reg_data *reg_data = cpuclk->reg_data;
183182
const struct rockchip_cpuclk_rate_table *rate;
184183
unsigned long flags;
184+
int i = 0;
185185

186186
rate = rockchip_get_cpuclk_settings(cpuclk, ndata->new_rate);
187187
if (!rate) {
@@ -202,12 +202,17 @@ static int rockchip_cpuclk_post_rate_change(struct rockchip_cpuclk *cpuclk,
202202
* primary parent by the extra dividers that were needed for the alt.
203203
*/
204204

205-
writel(HIWORD_UPDATE(0, reg_data->div_core_mask,
206-
reg_data->div_core_shift) |
207-
HIWORD_UPDATE(reg_data->mux_core_main,
208-
reg_data->mux_core_mask,
209-
reg_data->mux_core_shift),
210-
cpuclk->reg_base + reg_data->core_reg);
205+
writel(HIWORD_UPDATE(reg_data->mux_core_main,
206+
reg_data->mux_core_mask,
207+
reg_data->mux_core_shift),
208+
cpuclk->reg_base + reg_data->core_reg[0]);
209+
210+
/* remove dividers */
211+
for (i = 0; i < reg_data->num_cores; i++) {
212+
writel(HIWORD_UPDATE(0, reg_data->div_core_mask[i],
213+
reg_data->div_core_shift[i]),
214+
cpuclk->reg_base + reg_data->core_reg[i]);
215+
}
211216

212217
if (ndata->old_rate > ndata->new_rate)
213218
rockchip_cpuclk_set_dividers(cpuclk, rate);

‎drivers/clk/rockchip/clk-px30.c

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -124,9 +124,10 @@ static struct rockchip_cpuclk_rate_table px30_cpuclk_rates[] __initdata = {
124124
};
125125

126126
static const struct rockchip_cpuclk_reg_data px30_cpuclk_data = {
127-
.core_reg = PX30_CLKSEL_CON(0),
128-
.div_core_shift = 0,
129-
.div_core_mask = 0xf,
127+
.core_reg[0] = PX30_CLKSEL_CON(0),
128+
.div_core_shift[0] = 0,
129+
.div_core_mask[0] = 0xf,
130+
.num_cores = 1,
130131
.mux_core_alt = 1,
131132
.mux_core_main = 0,
132133
.mux_core_shift = 7,

‎drivers/clk/rockchip/clk-rk3036.c

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -102,9 +102,10 @@ static struct rockchip_cpuclk_rate_table rk3036_cpuclk_rates[] __initdata = {
102102
};
103103

104104
static const struct rockchip_cpuclk_reg_data rk3036_cpuclk_data = {
105-
.core_reg = RK2928_CLKSEL_CON(0),
106-
.div_core_shift = 0,
107-
.div_core_mask = 0x1f,
105+
.core_reg[0] = RK2928_CLKSEL_CON(0),
106+
.div_core_shift[0] = 0,
107+
.div_core_mask[0] = 0x1f,
108+
.num_cores = 1,
108109
.mux_core_alt = 1,
109110
.mux_core_main = 0,
110111
.mux_core_shift = 7,

‎drivers/clk/rockchip/clk-rk3128.c

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -117,9 +117,10 @@ static struct rockchip_cpuclk_rate_table rk3128_cpuclk_rates[] __initdata = {
117117
};
118118

119119
static const struct rockchip_cpuclk_reg_data rk3128_cpuclk_data = {
120-
.core_reg = RK2928_CLKSEL_CON(0),
121-
.div_core_shift = 0,
122-
.div_core_mask = 0x1f,
120+
.core_reg[0] = RK2928_CLKSEL_CON(0),
121+
.div_core_shift[0] = 0,
122+
.div_core_mask[0] = 0x1f,
123+
.num_cores = 1,
123124
.mux_core_alt = 1,
124125
.mux_core_main = 0,
125126
.mux_core_shift = 7,

‎drivers/clk/rockchip/clk-rk3188.c

Lines changed: 8 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -145,9 +145,10 @@ static struct rockchip_cpuclk_rate_table rk3066_cpuclk_rates[] __initdata = {
145145
};
146146

147147
static const struct rockchip_cpuclk_reg_data rk3066_cpuclk_data = {
148-
.core_reg = RK2928_CLKSEL_CON(0),
149-
.div_core_shift = 0,
150-
.div_core_mask = 0x1f,
148+
.core_reg[0] = RK2928_CLKSEL_CON(0),
149+
.div_core_shift[0] = 0,
150+
.div_core_mask[0] = 0x1f,
151+
.num_cores = 1,
151152
.mux_core_alt = 1,
152153
.mux_core_main = 0,
153154
.mux_core_shift = 8,
@@ -184,9 +185,10 @@ static struct rockchip_cpuclk_rate_table rk3188_cpuclk_rates[] __initdata = {
184185
};
185186

186187
static const struct rockchip_cpuclk_reg_data rk3188_cpuclk_data = {
187-
.core_reg = RK2928_CLKSEL_CON(0),
188-
.div_core_shift = 9,
189-
.div_core_mask = 0x1f,
188+
.core_reg[0] = RK2928_CLKSEL_CON(0),
189+
.div_core_shift[0] = 9,
190+
.div_core_mask[0] = 0x1f,
191+
.num_cores = 1,
190192
.mux_core_alt = 1,
191193
.mux_core_main = 0,
192194
.mux_core_shift = 8,

‎drivers/clk/rockchip/clk-rk3228.c

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -119,9 +119,10 @@ static struct rockchip_cpuclk_rate_table rk3228_cpuclk_rates[] __initdata = {
119119
};
120120

121121
static const struct rockchip_cpuclk_reg_data rk3228_cpuclk_data = {
122-
.core_reg = RK2928_CLKSEL_CON(0),
123-
.div_core_shift = 0,
124-
.div_core_mask = 0x1f,
122+
.core_reg[0] = RK2928_CLKSEL_CON(0),
123+
.div_core_shift[0] = 0,
124+
.div_core_mask[0] = 0x1f,
125+
.num_cores = 1,
125126
.mux_core_alt = 1,
126127
.mux_core_main = 0,
127128
.mux_core_shift = 6,

‎drivers/clk/rockchip/clk-rk3288.c

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -179,9 +179,10 @@ static struct rockchip_cpuclk_rate_table rk3288_cpuclk_rates[] __initdata = {
179179
};
180180

181181
static const struct rockchip_cpuclk_reg_data rk3288_cpuclk_data = {
182-
.core_reg = RK3288_CLKSEL_CON(0),
183-
.div_core_shift = 8,
184-
.div_core_mask = 0x1f,
182+
.core_reg[0] = RK3288_CLKSEL_CON(0),
183+
.div_core_shift[0] = 8,
184+
.div_core_mask[0] = 0x1f,
185+
.num_cores = 1,
185186
.mux_core_alt = 1,
186187
.mux_core_main = 0,
187188
.mux_core_shift = 15,

‎drivers/clk/rockchip/clk-rk3308.c

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -109,9 +109,10 @@ static struct rockchip_cpuclk_rate_table rk3308_cpuclk_rates[] __initdata = {
109109
};
110110

111111
static const struct rockchip_cpuclk_reg_data rk3308_cpuclk_data = {
112-
.core_reg = RK3308_CLKSEL_CON(0),
113-
.div_core_shift = 0,
114-
.div_core_mask = 0xf,
112+
.core_reg[0] = RK3308_CLKSEL_CON(0),
113+
.div_core_shift[0] = 0,
114+
.div_core_mask[0] = 0xf,
115+
.num_cores = 1,
115116
.mux_core_alt = 1,
116117
.mux_core_main = 0,
117118
.mux_core_shift = 6,

‎drivers/clk/rockchip/clk-rk3328.c

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -130,9 +130,10 @@ static struct rockchip_cpuclk_rate_table rk3328_cpuclk_rates[] __initdata = {
130130
};
131131

132132
static const struct rockchip_cpuclk_reg_data rk3328_cpuclk_data = {
133-
.core_reg = RK3328_CLKSEL_CON(0),
134-
.div_core_shift = 0,
135-
.div_core_mask = 0x1f,
133+
.core_reg[0] = RK3328_CLKSEL_CON(0),
134+
.div_core_shift[0] = 0,
135+
.div_core_mask[0] = 0x1f,
136+
.num_cores = 1,
136137
.mux_core_alt = 1,
137138
.mux_core_main = 3,
138139
.mux_core_shift = 6,

‎drivers/clk/rockchip/clk-rk3368.c

Lines changed: 8 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -154,21 +154,23 @@ static struct clk_div_table div_ddrphy_t[] = {
154154
#define IFLAGS ROCKCHIP_INVERTER_HIWORD_MASK
155155

156156
static const struct rockchip_cpuclk_reg_data rk3368_cpuclkb_data = {
157-
.core_reg = RK3368_CLKSEL_CON(0),
158-
.div_core_shift = 0,
159-
.div_core_mask = 0x1f,
157+
.core_reg[0] = RK3368_CLKSEL_CON(0),
158+
.div_core_shift[0] = 0,
159+
.div_core_mask[0] = 0x1f,
160+
.num_cores = 1,
160161
.mux_core_alt = 1,
161162
.mux_core_main = 0,
162163
.mux_core_shift = 7,
163164
.mux_core_mask = 0x1,
164165
};
165166

166167
static const struct rockchip_cpuclk_reg_data rk3368_cpuclkl_data = {
167-
.core_reg = RK3368_CLKSEL_CON(2),
168-
.div_core_shift = 0,
168+
.core_reg[0] = RK3368_CLKSEL_CON(2),
169+
.div_core_shift[0] = 0,
169170
.mux_core_alt = 1,
171+
.num_cores = 1,
170172
.mux_core_main = 0,
171-
.div_core_mask = 0x1f,
173+
.div_core_mask[0] = 0x1f,
172174
.mux_core_shift = 7,
173175
.mux_core_mask = 0x1,
174176
};

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