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Nicholas Kazlauskasalexdeucher
Nicholas Kazlauskas
authored and
alexdeucher
committed
drm/amd/display: Query VCO frequency from register for DCN3.1
[Why] Hardcoding the VCO frequency isn't correct since we don't own or control the value. In the case where the hardcode is also missing we can't lightup display. [How] Query from the CLK register instead. Update the DFS frequency to be able to compute the VCO frequency. Reviewed-by: Eric Yang <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Nicholas Kazlauskas <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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-55
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‎drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

Lines changed: 42 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -48,6 +48,21 @@
4848

4949
#include "dc_dmub_srv.h"
5050

51+
#include "yellow_carp_offset.h"
52+
53+
#define regCLK1_CLK_PLL_REQ 0x0237
54+
#define regCLK1_CLK_PLL_REQ_BASE_IDX 0
55+
56+
#define CLK1_CLK_PLL_REQ__FbMult_int__SHIFT 0x0
57+
#define CLK1_CLK_PLL_REQ__PllSpineDiv__SHIFT 0xc
58+
#define CLK1_CLK_PLL_REQ__FbMult_frac__SHIFT 0x10
59+
#define CLK1_CLK_PLL_REQ__FbMult_int_MASK 0x000001FFL
60+
#define CLK1_CLK_PLL_REQ__PllSpineDiv_MASK 0x0000F000L
61+
#define CLK1_CLK_PLL_REQ__FbMult_frac_MASK 0xFFFF0000L
62+
63+
#define REG(reg_name) \
64+
(CLK_BASE.instance[0].segment[reg ## reg_name ## _BASE_IDX] + reg ## reg_name)
65+
5166
#define TO_CLK_MGR_DCN31(clk_mgr)\
5267
container_of(clk_mgr, struct clk_mgr_dcn31, base)
5368

@@ -229,7 +244,32 @@ static void dcn31_update_clocks(struct clk_mgr *clk_mgr_base,
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230245
static int get_vco_frequency_from_reg(struct clk_mgr_internal *clk_mgr)
231246
{
232-
return 0;
247+
/* get FbMult value */
248+
struct fixed31_32 pll_req;
249+
unsigned int fbmult_frac_val = 0;
250+
unsigned int fbmult_int_val = 0;
251+
252+
/*
253+
* Register value of fbmult is in 8.16 format, we are converting to 31.32
254+
* to leverage the fix point operations available in driver
255+
*/
256+
257+
REG_GET(CLK1_CLK_PLL_REQ, FbMult_frac, &fbmult_frac_val); /* 16 bit fractional part*/
258+
REG_GET(CLK1_CLK_PLL_REQ, FbMult_int, &fbmult_int_val); /* 8 bit integer part */
259+
260+
pll_req = dc_fixpt_from_int(fbmult_int_val);
261+
262+
/*
263+
* since fractional part is only 16 bit in register definition but is 32 bit
264+
* in our fix point definiton, need to shift left by 16 to obtain correct value
265+
*/
266+
pll_req.value |= fbmult_frac_val << 16;
267+
268+
/* multiply by REFCLK period */
269+
pll_req = dc_fixpt_mul_int(pll_req, clk_mgr->dfs_ref_freq_khz);
270+
271+
/* integer part is now VCO frequency in kHz */
272+
return dc_fixpt_floor(pll_req);
233273
}
234274

235275
static void dcn31_enable_pme_wa(struct clk_mgr *clk_mgr_base)
@@ -592,6 +632,7 @@ void dcn31_clk_mgr_construct(
592632
clk_mgr->base.dprefclk_ss_percentage = 0;
593633
clk_mgr->base.dprefclk_ss_divider = 1000;
594634
clk_mgr->base.ss_on_dprefclk = false;
635+
clk_mgr->base.dfs_ref_freq_khz = 48000;
595636

596637
clk_mgr->smu_wm_set.wm_set = (struct dcn31_watermarks *)dm_helpers_allocate_gpu_mem(
597638
clk_mgr->base.base.ctx,

‎drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.h

Lines changed: 0 additions & 54 deletions
Original file line numberDiff line numberDiff line change
@@ -27,60 +27,6 @@
2727
#define __DCN31_CLK_MGR_H__
2828
#include "clk_mgr_internal.h"
2929

30-
//CLK1_CLK_PLL_REQ
31-
#ifndef CLK11_CLK1_CLK_PLL_REQ__FbMult_int__SHIFT
32-
#define CLK11_CLK1_CLK_PLL_REQ__FbMult_int__SHIFT 0x0
33-
#define CLK11_CLK1_CLK_PLL_REQ__PllSpineDiv__SHIFT 0xc
34-
#define CLK11_CLK1_CLK_PLL_REQ__FbMult_frac__SHIFT 0x10
35-
#define CLK11_CLK1_CLK_PLL_REQ__FbMult_int_MASK 0x000001FFL
36-
#define CLK11_CLK1_CLK_PLL_REQ__PllSpineDiv_MASK 0x0000F000L
37-
#define CLK11_CLK1_CLK_PLL_REQ__FbMult_frac_MASK 0xFFFF0000L
38-
//CLK1_CLK0_DFS_CNTL
39-
#define CLK11_CLK1_CLK0_DFS_CNTL__CLK0_DIVIDER__SHIFT 0x0
40-
#define CLK11_CLK1_CLK0_DFS_CNTL__CLK0_DIVIDER_MASK 0x0000007FL
41-
/*DPREF clock related*/
42-
#define CLK0_CLK3_DFS_CNTL__CLK3_DIVIDER__SHIFT 0x0
43-
#define CLK0_CLK3_DFS_CNTL__CLK3_DIVIDER_MASK 0x0000007FL
44-
#define CLK1_CLK3_DFS_CNTL__CLK3_DIVIDER__SHIFT 0x0
45-
#define CLK1_CLK3_DFS_CNTL__CLK3_DIVIDER_MASK 0x0000007FL
46-
#define CLK2_CLK3_DFS_CNTL__CLK3_DIVIDER__SHIFT 0x0
47-
#define CLK2_CLK3_DFS_CNTL__CLK3_DIVIDER_MASK 0x0000007FL
48-
#define CLK3_CLK3_DFS_CNTL__CLK3_DIVIDER__SHIFT 0x0
49-
#define CLK3_CLK3_DFS_CNTL__CLK3_DIVIDER_MASK 0x0000007FL
50-
51-
//CLK3_0_CLK3_CLK_PLL_REQ
52-
#define CLK3_0_CLK3_CLK_PLL_REQ__FbMult_int__SHIFT 0x0
53-
#define CLK3_0_CLK3_CLK_PLL_REQ__PllSpineDiv__SHIFT 0xc
54-
#define CLK3_0_CLK3_CLK_PLL_REQ__FbMult_frac__SHIFT 0x10
55-
#define CLK3_0_CLK3_CLK_PLL_REQ__FbMult_int_MASK 0x000001FFL
56-
#define CLK3_0_CLK3_CLK_PLL_REQ__PllSpineDiv_MASK 0x0000F000L
57-
#define CLK3_0_CLK3_CLK_PLL_REQ__FbMult_frac_MASK 0xFFFF0000L
58-
59-
#define mmCLK0_CLK3_DFS_CNTL 0x16C60
60-
#define mmCLK00_CLK0_CLK3_DFS_CNTL 0x16C60
61-
#define mmCLK01_CLK0_CLK3_DFS_CNTL 0x16E60
62-
#define mmCLK02_CLK0_CLK3_DFS_CNTL 0x17060
63-
#define mmCLK03_CLK0_CLK3_DFS_CNTL 0x17260
64-
65-
#define mmCLK0_CLK_PLL_REQ 0x16C10
66-
#define mmCLK00_CLK0_CLK_PLL_REQ 0x16C10
67-
#define mmCLK01_CLK0_CLK_PLL_REQ 0x16E10
68-
#define mmCLK02_CLK0_CLK_PLL_REQ 0x17010
69-
#define mmCLK03_CLK0_CLK_PLL_REQ 0x17210
70-
71-
#define mmCLK1_CLK_PLL_REQ 0x1B00D
72-
#define mmCLK10_CLK1_CLK_PLL_REQ 0x1B00D
73-
#define mmCLK11_CLK1_CLK_PLL_REQ 0x1B20D
74-
#define mmCLK12_CLK1_CLK_PLL_REQ 0x1B40D
75-
#define mmCLK13_CLK1_CLK_PLL_REQ 0x1B60D
76-
77-
#define mmCLK2_CLK_PLL_REQ 0x17E0D
78-
79-
/*AMCLK*/
80-
#define mmCLK11_CLK1_CLK0_DFS_CNTL 0x1B23F
81-
#define mmCLK11_CLK1_CLK_PLL_REQ 0x1B20D
82-
#endif
83-
8430
struct dcn31_watermarks;
8531

8632
struct dcn31_smu_watermark_set {

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