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torvaldstorvalds
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Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull more clk updates from Stephen Boyd: - A handful of fixes for lmk04832 driver - Migrate the basic clk divider to use determine rate ops - Fix modpost build for hisilicon hi3559a driver - Actually set the parent in k210_clk_set_parent() * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: Revert "clk: divider: Switch from .round_rate to .determine_rate by default" clk: hisilicon: hi3559a: Drop __init markings everywhere clk: meson: regmap: switch to determine_rate for the dividers clk: divider: Switch from .round_rate to .determine_rate by default clk: divider: Add re-usable determine_rate implementations clk: k210: Fix k210_clk_set_parent() clk: lmk04832: Fix spelling mistakes in dev_err messages and comments clk: lmk04832: fix return value check in lmk04832_probe() clk: stm32mp1: fix missing spin_lock_init()
2 parents 316a2c9 + 783d08b commit b0dfd9a

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7 files changed

+107
-54
lines changed

7 files changed

+107
-54
lines changed

‎drivers/clk/clk-divider.c

Lines changed: 61 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -343,16 +343,63 @@ static int clk_divider_bestdiv(struct clk_hw *hw, struct clk_hw *parent,
343343
return bestdiv;
344344
}
345345

346+
int divider_determine_rate(struct clk_hw *hw, struct clk_rate_request *req,
347+
const struct clk_div_table *table, u8 width,
348+
unsigned long flags)
349+
{
350+
int div;
351+
352+
div = clk_divider_bestdiv(hw, req->best_parent_hw, req->rate,
353+
&req->best_parent_rate, table, width, flags);
354+
355+
req->rate = DIV_ROUND_UP_ULL((u64)req->best_parent_rate, div);
356+
357+
return 0;
358+
}
359+
EXPORT_SYMBOL_GPL(divider_determine_rate);
360+
361+
int divider_ro_determine_rate(struct clk_hw *hw, struct clk_rate_request *req,
362+
const struct clk_div_table *table, u8 width,
363+
unsigned long flags, unsigned int val)
364+
{
365+
int div;
366+
367+
div = _get_div(table, val, flags, width);
368+
369+
/* Even a read-only clock can propagate a rate change */
370+
if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) {
371+
if (!req->best_parent_hw)
372+
return -EINVAL;
373+
374+
req->best_parent_rate = clk_hw_round_rate(req->best_parent_hw,
375+
req->rate * div);
376+
}
377+
378+
req->rate = DIV_ROUND_UP_ULL((u64)req->best_parent_rate, div);
379+
380+
return 0;
381+
}
382+
EXPORT_SYMBOL_GPL(divider_ro_determine_rate);
383+
346384
long divider_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent,
347385
unsigned long rate, unsigned long *prate,
348386
const struct clk_div_table *table,
349387
u8 width, unsigned long flags)
350388
{
351-
int div;
389+
struct clk_rate_request req = {
390+
.rate = rate,
391+
.best_parent_rate = *prate,
392+
.best_parent_hw = parent,
393+
};
394+
int ret;
352395

353-
div = clk_divider_bestdiv(hw, parent, rate, prate, table, width, flags);
396+
ret = divider_determine_rate(hw, &req, table, width, flags);
397+
if (ret)
398+
return ret;
354399

355-
return DIV_ROUND_UP_ULL((u64)*prate, div);
400+
*prate = req.best_parent_rate;
401+
402+
return req.rate;
356403
}
357404
EXPORT_SYMBOL_GPL(divider_round_rate_parent);
358405

@@ -361,23 +408,23 @@ long divider_ro_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent,
361408
const struct clk_div_table *table, u8 width,
362409
unsigned long flags, unsigned int val)
363410
{
364-
int div;
365-
366-
div = _get_div(table, val, flags, width);
411+
struct clk_rate_request req = {
412+
.rate = rate,
413+
.best_parent_rate = *prate,
414+
.best_parent_hw = parent,
415+
};
416+
int ret;
367417

368-
/* Even a read-only clock can propagate a rate change */
369-
if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) {
370-
if (!parent)
371-
return -EINVAL;
418+
ret = divider_ro_determine_rate(hw, &req, table, width, flags, val);
419+
if (ret)
420+
return ret;
372421

373-
*prate = clk_hw_round_rate(parent, rate * div);
374-
}
422+
*prate = req.best_parent_rate;
375423

376-
return DIV_ROUND_UP_ULL((u64)*prate, div);
424+
return req.rate;
377425
}
378426
EXPORT_SYMBOL_GPL(divider_ro_round_rate_parent);
379427

380-
381428
static long clk_divider_round_rate(struct clk_hw *hw, unsigned long rate,
382429
unsigned long *prate)
383430
{

‎drivers/clk/clk-k210.c

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -722,6 +722,7 @@ static int k210_clk_set_parent(struct clk_hw *hw, u8 index)
722722
reg |= BIT(cfg->mux_bit);
723723
else
724724
reg &= ~BIT(cfg->mux_bit);
725+
writel(reg, ksc->regs + cfg->mux_reg);
725726
spin_unlock_irqrestore(&ksc->clk_lock, flags);
726727

727728
return 0;

‎drivers/clk/clk-lmk04832.c

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -519,7 +519,7 @@ static long lmk04832_vco_round_rate(struct clk_hw *hw, unsigned long rate,
519519

520520
vco_rate = lmk04832_calc_pll2_params(*prate, rate, &n, &p, &r);
521521
if (vco_rate < 0) {
522-
dev_err(lmk->dev, "PLL2 parmeters out of range\n");
522+
dev_err(lmk->dev, "PLL2 parameters out of range\n");
523523
return vco_rate;
524524
}
525525

@@ -550,7 +550,7 @@ static int lmk04832_vco_set_rate(struct clk_hw *hw, unsigned long rate,
550550

551551
vco_rate = lmk04832_calc_pll2_params(prate, rate, &n, &p, &r);
552552
if (vco_rate < 0) {
553-
dev_err(lmk->dev, "failed to determine PLL2 parmeters\n");
553+
dev_err(lmk->dev, "failed to determine PLL2 parameters\n");
554554
return vco_rate;
555555
}
556556

@@ -573,7 +573,7 @@ static int lmk04832_vco_set_rate(struct clk_hw *hw, unsigned long rate,
573573

574574
/*
575575
* PLL2_N registers must be programmed after other PLL2 dividers are
576-
* programed to ensure proper VCO frequency calibration
576+
* programmed to ensure proper VCO frequency calibration
577577
*/
578578
ret = regmap_write(lmk->regmap, LMK04832_REG_PLL2_N_0,
579579
FIELD_GET(0x030000, n));
@@ -1120,7 +1120,7 @@ static int lmk04832_dclk_set_rate(struct clk_hw *hw, unsigned long rate,
11201120
return -EINVAL;
11211121
}
11221122

1123-
/* Enable Duty Cycle Corretion */
1123+
/* Enable Duty Cycle Correction */
11241124
if (dclk_div == 1) {
11251125
ret = regmap_update_bits(lmk->regmap,
11261126
LMK04832_REG_CLKOUT_CTRL3(dclk->id),
@@ -1425,23 +1425,23 @@ static int lmk04832_probe(struct spi_device *spi)
14251425

14261426
lmk->dclk = devm_kcalloc(lmk->dev, info->num_channels >> 1,
14271427
sizeof(struct lmk_dclk), GFP_KERNEL);
1428-
if (IS_ERR(lmk->dclk)) {
1429-
ret = PTR_ERR(lmk->dclk);
1428+
if (!lmk->dclk) {
1429+
ret = -ENOMEM;
14301430
goto err_disable_oscin;
14311431
}
14321432

14331433
lmk->clkout = devm_kcalloc(lmk->dev, info->num_channels,
14341434
sizeof(*lmk->clkout), GFP_KERNEL);
1435-
if (IS_ERR(lmk->clkout)) {
1436-
ret = PTR_ERR(lmk->clkout);
1435+
if (!lmk->clkout) {
1436+
ret = -ENOMEM;
14371437
goto err_disable_oscin;
14381438
}
14391439

14401440
lmk->clk_data = devm_kzalloc(lmk->dev, struct_size(lmk->clk_data, hws,
14411441
info->num_channels),
14421442
GFP_KERNEL);
1443-
if (IS_ERR(lmk->clk_data)) {
1444-
ret = PTR_ERR(lmk->clk_data);
1443+
if (!lmk->clk_data) {
1444+
ret = -ENOMEM;
14451445
goto err_disable_oscin;
14461446
}
14471447

‎drivers/clk/clk-stm32mp1.c

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2263,6 +2263,7 @@ static int stm32_rcc_reset_init(struct device *dev, void __iomem *base,
22632263
if (!reset_data)
22642264
return -ENOMEM;
22652265

2266+
spin_lock_init(&reset_data->lock);
22662267
reset_data->membase = base;
22672268
reset_data->rcdev.owner = THIS_MODULE;
22682269
reset_data->rcdev.ops = &stm32_reset_ops;

‎drivers/clk/hisilicon/clk-hi3559a.c

Lines changed: 19 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -107,25 +107,25 @@ static const struct hisi_fixed_rate_clock hi3559av100_fixed_rate_clks_crg[] = {
107107
};
108108

109109

110-
static const char *fmc_mux_p[] __initconst = {
110+
static const char *fmc_mux_p[] = {
111111
"24m", "75m", "125m", "150m", "200m", "250m", "300m", "400m"
112112
};
113113

114-
static const char *mmc_mux_p[] __initconst = {
114+
static const char *mmc_mux_p[] = {
115115
"100k", "25m", "49p5m", "99m", "187p5m", "150m", "198m", "400k"
116116
};
117117

118-
static const char *sysapb_mux_p[] __initconst = {
118+
static const char *sysapb_mux_p[] = {
119119
"24m", "50m",
120120
};
121121

122-
static const char *sysbus_mux_p[] __initconst = {
122+
static const char *sysbus_mux_p[] = {
123123
"24m", "300m"
124124
};
125125

126-
static const char *uart_mux_p[] __initconst = { "50m", "24m", "3m" };
126+
static const char *uart_mux_p[] = { "50m", "24m", "3m" };
127127

128-
static const char *a73_clksel_mux_p[] __initconst = {
128+
static const char *a73_clksel_mux_p[] = {
129129
"24m", "apll", "1000m"
130130
};
131131

@@ -136,7 +136,7 @@ static const u32 sysbus_mux_table[] = { 0, 1 };
136136
static const u32 uart_mux_table[] = { 0, 1, 2 };
137137
static const u32 a73_clksel_mux_table[] = { 0, 1, 2 };
138138

139-
static struct hisi_mux_clock hi3559av100_mux_clks_crg[] __initdata = {
139+
static struct hisi_mux_clock hi3559av100_mux_clks_crg[] = {
140140
{
141141
HI3559AV100_FMC_MUX, "fmc_mux", fmc_mux_p, ARRAY_SIZE(fmc_mux_p),
142142
CLK_SET_RATE_PARENT, 0x170, 2, 3, 0, fmc_mux_table,
@@ -181,7 +181,7 @@ static struct hisi_mux_clock hi3559av100_mux_clks_crg[] __initdata = {
181181
},
182182
};
183183

184-
static struct hisi_gate_clock hi3559av100_gate_clks[] __initdata = {
184+
static struct hisi_gate_clock hi3559av100_gate_clks[] = {
185185
{
186186
HI3559AV100_FMC_CLK, "clk_fmc", "fmc_mux",
187187
CLK_SET_RATE_PARENT, 0x170, 1, 0,
@@ -336,7 +336,7 @@ static struct hisi_gate_clock hi3559av100_gate_clks[] __initdata = {
336336
},
337337
};
338338

339-
static struct hi3559av100_pll_clock hi3559av100_pll_clks[] __initdata = {
339+
static struct hi3559av100_pll_clock hi3559av100_pll_clks[] = {
340340
{
341341
HI3559AV100_APLL_CLK, "apll", NULL, 0x0, 0, 24, 24, 3, 28, 3,
342342
0x4, 0, 12, 12, 6
@@ -502,7 +502,7 @@ static void hisi_clk_register_pll(struct hi3559av100_pll_clock *clks,
502502
}
503503
}
504504

505-
static __init struct hisi_clock_data *hi3559av100_clk_register(
505+
static struct hisi_clock_data *hi3559av100_clk_register(
506506
struct platform_device *pdev)
507507
{
508508
struct hisi_clock_data *clk_data;
@@ -549,7 +549,7 @@ static __init struct hisi_clock_data *hi3559av100_clk_register(
549549
return ERR_PTR(ret);
550550
}
551551

552-
static __init void hi3559av100_clk_unregister(struct platform_device *pdev)
552+
static void hi3559av100_clk_unregister(struct platform_device *pdev)
553553
{
554554
struct hisi_crg_dev *crg = platform_get_drvdata(pdev);
555555

@@ -568,8 +568,7 @@ static const struct hisi_crg_funcs hi3559av100_crg_funcs = {
568568
.unregister_clks = hi3559av100_clk_unregister,
569569
};
570570

571-
static struct hisi_fixed_rate_clock hi3559av100_shub_fixed_rate_clks[]
572-
__initdata = {
571+
static struct hisi_fixed_rate_clock hi3559av100_shub_fixed_rate_clks[] = {
573572
{ HI3559AV100_SHUB_SOURCE_SOC_24M, "clk_source_24M", NULL, 0, 24000000UL, },
574573
{ HI3559AV100_SHUB_SOURCE_SOC_200M, "clk_source_200M", NULL, 0, 200000000UL, },
575574
{ HI3559AV100_SHUB_SOURCE_SOC_300M, "clk_source_300M", NULL, 0, 300000000UL, },
@@ -587,16 +586,16 @@ static struct hisi_fixed_rate_clock hi3559av100_shub_fixed_rate_clks[]
587586

588587
/* shub mux clk */
589588
static u32 shub_source_clk_mux_table[] = {0, 1, 2, 3};
590-
static const char *shub_source_clk_mux_p[] __initconst = {
589+
static const char *shub_source_clk_mux_p[] = {
591590
"clk_source_24M", "clk_source_200M", "clk_source_300M", "clk_source_PLL"
592591
};
593592

594593
static u32 shub_uart_source_clk_mux_table[] = {0, 1, 2, 3};
595-
static const char *shub_uart_source_clk_mux_p[] __initconst = {
594+
static const char *shub_uart_source_clk_mux_p[] = {
596595
"clk_uart_32K", "clk_uart_div_clk", "clk_uart_div_clk", "clk_source_24M"
597596
};
598597

599-
static struct hisi_mux_clock hi3559av100_shub_mux_clks[] __initdata = {
598+
static struct hisi_mux_clock hi3559av100_shub_mux_clks[] = {
600599
{
601600
HI3559AV100_SHUB_SOURCE_CLK, "shub_clk", shub_source_clk_mux_p,
602601
ARRAY_SIZE(shub_source_clk_mux_p),
@@ -615,7 +614,7 @@ static struct hisi_mux_clock hi3559av100_shub_mux_clks[] __initdata = {
615614
static struct clk_div_table shub_spi_clk_table[] = {{0, 8}, {1, 4}, {2, 2}};
616615
static struct clk_div_table shub_uart_div_clk_table[] = {{1, 8}, {2, 4}};
617616

618-
static struct hisi_divider_clock hi3559av100_shub_div_clks[] __initdata = {
617+
static struct hisi_divider_clock hi3559av100_shub_div_clks[] = {
619618
{ HI3559AV100_SHUB_SPI_SOURCE_CLK, "clk_spi_clk", "shub_clk", 0, 0x20, 24, 2,
620619
CLK_DIVIDER_ALLOW_ZERO, shub_spi_clk_table,
621620
},
@@ -625,7 +624,7 @@ static struct hisi_divider_clock hi3559av100_shub_div_clks[] __initdata = {
625624
};
626625

627626
/* shub gate clk */
628-
static struct hisi_gate_clock hi3559av100_shub_gate_clks[] __initdata = {
627+
static struct hisi_gate_clock hi3559av100_shub_gate_clks[] = {
629628
{
630629
HI3559AV100_SHUB_SPI0_CLK, "clk_shub_spi0", "clk_spi_clk",
631630
0, 0x20, 1, 0,
@@ -697,7 +696,7 @@ static int hi3559av100_shub_default_clk_set(void)
697696
return 0;
698697
}
699698

700-
static __init struct hisi_clock_data *hi3559av100_shub_clk_register(
699+
static struct hisi_clock_data *hi3559av100_shub_clk_register(
701700
struct platform_device *pdev)
702701
{
703702
struct hisi_clock_data *clk_data = NULL;
@@ -751,7 +750,7 @@ static __init struct hisi_clock_data *hi3559av100_shub_clk_register(
751750
return ERR_PTR(ret);
752751
}
753752

754-
static __init void hi3559av100_shub_clk_unregister(struct platform_device *pdev)
753+
static void hi3559av100_shub_clk_unregister(struct platform_device *pdev)
755754
{
756755
struct hisi_crg_dev *crg = platform_get_drvdata(pdev);
757756

‎drivers/clk/meson/clk-regmap.c

Lines changed: 9 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -75,8 +75,8 @@ static unsigned long clk_regmap_div_recalc_rate(struct clk_hw *hw,
7575
div->width);
7676
}
7777

78-
static long clk_regmap_div_round_rate(struct clk_hw *hw, unsigned long rate,
79-
unsigned long *prate)
78+
static int clk_regmap_div_determine_rate(struct clk_hw *hw,
79+
struct clk_rate_request *req)
8080
{
8181
struct clk_regmap *clk = to_clk_regmap(hw);
8282
struct clk_regmap_div_data *div = clk_get_regmap_div_data(clk);
@@ -87,18 +87,17 @@ static long clk_regmap_div_round_rate(struct clk_hw *hw, unsigned long rate,
8787
if (div->flags & CLK_DIVIDER_READ_ONLY) {
8888
ret = regmap_read(clk->map, div->offset, &val);
8989
if (ret)
90-
/* Gives a hint that something is wrong */
91-
return 0;
90+
return ret;
9291

9392
val >>= div->shift;
9493
val &= clk_div_mask(div->width);
9594

96-
return divider_ro_round_rate(hw, rate, prate, div->table,
97-
div->width, div->flags, val);
95+
return divider_ro_determine_rate(hw, req, div->table,
96+
div->width, div->flags, val);
9897
}
9998

100-
return divider_round_rate(hw, rate, prate, div->table, div->width,
101-
div->flags);
99+
return divider_determine_rate(hw, req, div->table, div->width,
100+
div->flags);
102101
}
103102

104103
static int clk_regmap_div_set_rate(struct clk_hw *hw, unsigned long rate,
@@ -123,14 +122,14 @@ static int clk_regmap_div_set_rate(struct clk_hw *hw, unsigned long rate,
123122

124123
const struct clk_ops clk_regmap_divider_ops = {
125124
.recalc_rate = clk_regmap_div_recalc_rate,
126-
.round_rate = clk_regmap_div_round_rate,
125+
.determine_rate = clk_regmap_div_determine_rate,
127126
.set_rate = clk_regmap_div_set_rate,
128127
};
129128
EXPORT_SYMBOL_GPL(clk_regmap_divider_ops);
130129

131130
const struct clk_ops clk_regmap_divider_ro_ops = {
132131
.recalc_rate = clk_regmap_div_recalc_rate,
133-
.round_rate = clk_regmap_div_round_rate,
132+
.determine_rate = clk_regmap_div_determine_rate,
134133
};
135134
EXPORT_SYMBOL_GPL(clk_regmap_divider_ro_ops);
136135

‎include/linux/clk-provider.h

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -629,6 +629,12 @@ long divider_ro_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent,
629629
unsigned long rate, unsigned long *prate,
630630
const struct clk_div_table *table, u8 width,
631631
unsigned long flags, unsigned int val);
632+
int divider_determine_rate(struct clk_hw *hw, struct clk_rate_request *req,
633+
const struct clk_div_table *table, u8 width,
634+
unsigned long flags);
635+
int divider_ro_determine_rate(struct clk_hw *hw, struct clk_rate_request *req,
636+
const struct clk_div_table *table, u8 width,
637+
unsigned long flags, unsigned int val);
632638
int divider_get_val(unsigned long rate, unsigned long parent_rate,
633639
const struct clk_div_table *table, u8 width,
634640
unsigned long flags);

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