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Fabrice Gasnierjic23
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counter: stm32-timer-cnt: fix ceiling miss-alignment with reload register
Ceiling value may be miss-aligned with what's actually configured into the ARR register. This is seen after probe as currently the ARR value is zero, whereas ceiling value is set to the maximum. So: - reading ceiling reports zero - in case the counter gets enabled without any prior configuration, it won't count. - in case the function gets set by the user 1st, (priv->ceiling) is used. Fix it by getting rid of the cached "priv->ceiling" variable. Rather use the ARR register value directly by using regmap read or write when needed. There should be no drawback on performance as priv->ceiling isn't used in performance critical path. There's also no point in writing ARR while setting function (sms), so it can be safely removed. Fixes: ad29937 ("counter: Add STM32 Timer quadrature encoder") Suggested-by: William Breathitt Gray <[email protected]> Signed-off-by: Fabrice Gasnier <[email protected]> Acked-by: William Breathitt Gray <[email protected]> Cc: <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Jonathan Cameron <[email protected]>
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drivers/counter/stm32-timer-cnt.c

Lines changed: 3 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -31,7 +31,6 @@ struct stm32_timer_cnt {
3131
struct counter_device counter;
3232
struct regmap *regmap;
3333
struct clk *clk;
34-
u32 ceiling;
3534
u32 max_arr;
3635
bool enabled;
3736
struct stm32_timer_regs bak;
@@ -75,8 +74,10 @@ static int stm32_count_write(struct counter_device *counter,
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const unsigned long val)
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{
7776
struct stm32_timer_cnt *const priv = counter->priv;
77+
u32 ceiling;
7878

79-
if (val > priv->ceiling)
79+
regmap_read(priv->regmap, TIM_ARR, &ceiling);
80+
if (val > ceiling)
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return -EINVAL;
8182

8283
return regmap_write(priv->regmap, TIM_CNT, val);
@@ -138,10 +139,6 @@ static int stm32_count_function_set(struct counter_device *counter,
138139

139140
regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0);
140141

141-
/* TIMx_ARR register shouldn't be buffered (ARPE=0) */
142-
regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE, 0);
143-
regmap_write(priv->regmap, TIM_ARR, priv->ceiling);
144-
145142
regmap_update_bits(priv->regmap, TIM_SMCR, TIM_SMCR_SMS, sms);
146143

147144
/* Make sure that registers are updated */
@@ -199,7 +196,6 @@ static ssize_t stm32_count_ceiling_write(struct counter_device *counter,
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regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE, 0);
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regmap_write(priv->regmap, TIM_ARR, ceiling);
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202-
priv->ceiling = ceiling;
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return len;
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}
205201

@@ -374,7 +370,6 @@ static int stm32_timer_cnt_probe(struct platform_device *pdev)
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375371
priv->regmap = ddata->regmap;
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priv->clk = ddata->clk;
377-
priv->ceiling = ddata->max_arr;
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priv->max_arr = ddata->max_arr;
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380375
priv->counter.name = dev_name(dev);

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