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geertugeertu
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pinctrl: renesas: r8a77970: Add bias pinconf support
Implement support for pull-up (most pins, excl. DU_DOTCLKIN and EXTALR) and pull-down (most pins, excl. JTAG) handling for the R-Car V3M SoC, using the common R-Car bias handling. Signed-off-by: Geert Uytterhoeven <[email protected]> Reviewed-by: Niklas Söderlund <[email protected]> Link: https://lore.kernel.org/r/bcfad447624d874258a45a92554574b8fe9f712f.1619785375.git.geert+renesas@glider.be
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‎drivers/pinctrl/renesas/pfc-r8a77970.c

Lines changed: 169 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -19,12 +19,23 @@
1919
#include "sh_pfc.h"
2020

2121
#define CPU_ALL_GP(fn, sfx) \
22-
PORT_GP_CFG_22(0, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
23-
PORT_GP_28(1, fn, sfx), \
24-
PORT_GP_CFG_17(2, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
25-
PORT_GP_CFG_17(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
26-
PORT_GP_6(4, fn, sfx), \
27-
PORT_GP_15(5, fn, sfx)
22+
PORT_GP_CFG_22(0, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP_DOWN), \
23+
PORT_GP_CFG_28(1, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
24+
PORT_GP_CFG_17(2, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP_DOWN), \
25+
PORT_GP_CFG_17(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP_DOWN), \
26+
PORT_GP_CFG_6(4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
27+
PORT_GP_CFG_15(5, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN)
28+
29+
#define CPU_ALL_NOGP(fn) \
30+
PIN_NOGP_CFG(DU_DOTCLKIN, "DU_DOTCLKIN", fn, SH_PFC_PIN_CFG_PULL_DOWN), \
31+
PIN_NOGP_CFG(EXTALR, "EXTALR", fn, SH_PFC_PIN_CFG_PULL_DOWN), \
32+
PIN_NOGP_CFG(FSCLKST_N, "FSCLKST#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
33+
PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
34+
PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP), \
35+
PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP), \
36+
PIN_NOGP_CFG(TMS, "TMS", fn, SH_PFC_PIN_CFG_PULL_UP), \
37+
PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP)
38+
2839
/*
2940
* F_() : just information
3041
* FM() : macro for FN_xxx / xxx_MARK
@@ -718,8 +729,17 @@ static const u16 pinmux_data[] = {
718729
PINMUX_IPSR_GPSR(IP8_27_24, DIGRF_CLKEN_OUT),
719730
};
720731

732+
/*
733+
* Pins not associated with a GPIO port.
734+
*/
735+
enum {
736+
GP_ASSIGN_LAST(),
737+
NOGP_ALL(),
738+
};
739+
721740
static const struct sh_pfc_pin pinmux_pins[] = {
722741
PINMUX_GPIO_GP_ALL(),
742+
PINMUX_NOGP_ALL(),
723743
};
724744

725745
/* - AVB0 ------------------------------------------------------------------- */
@@ -2496,8 +2516,150 @@ static int r8a77970_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin,
24962516
return -EINVAL;
24972517
}
24982518

2519+
static const struct pinmux_bias_reg pinmux_bias_regs[] = {
2520+
{ PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) {
2521+
[ 0] = RCAR_GP_PIN(0, 0), /* DU_DR2 */
2522+
[ 1] = RCAR_GP_PIN(0, 1), /* DU_DR3 */
2523+
[ 2] = RCAR_GP_PIN(0, 2), /* DU_DR4 */
2524+
[ 3] = RCAR_GP_PIN(0, 3), /* DU_DR5 */
2525+
[ 4] = RCAR_GP_PIN(0, 4), /* DU_DR6 */
2526+
[ 5] = RCAR_GP_PIN(0, 5), /* DU_DR7 */
2527+
[ 6] = RCAR_GP_PIN(0, 6), /* DU_DG2 */
2528+
[ 7] = RCAR_GP_PIN(0, 7), /* DU_DG3 */
2529+
[ 8] = RCAR_GP_PIN(0, 8), /* DU_DG4 */
2530+
[ 9] = RCAR_GP_PIN(0, 9), /* DU_DG5 */
2531+
[10] = RCAR_GP_PIN(0, 10), /* DU_DG6 */
2532+
[11] = RCAR_GP_PIN(0, 11), /* DU_DG7 */
2533+
[12] = RCAR_GP_PIN(0, 12), /* DU_DB2 */
2534+
[13] = RCAR_GP_PIN(0, 13), /* DU_DB3 */
2535+
[14] = RCAR_GP_PIN(0, 14), /* DU_DB4 */
2536+
[15] = RCAR_GP_PIN(0, 15), /* DU_DB5 */
2537+
[16] = RCAR_GP_PIN(0, 16), /* DU_DB6 */
2538+
[17] = RCAR_GP_PIN(0, 17), /* DU_DB7 */
2539+
[18] = RCAR_GP_PIN(0, 18), /* DU_DOTCLKOUT */
2540+
[19] = RCAR_GP_PIN(0, 19), /* DU_EXHSYNC/DU_HSYNC */
2541+
[20] = RCAR_GP_PIN(0, 20), /* DU_EXVSYNC/DU_VSYNC */
2542+
[21] = RCAR_GP_PIN(0, 21), /* DU_EXODDF/DU_ODDF/DISP/CDE */
2543+
[22] = PIN_DU_DOTCLKIN, /* DU_DOTCLKIN */
2544+
[23] = PIN_PRESETOUT_N, /* PRESETOUT# */
2545+
[24] = PIN_EXTALR, /* EXTALR */
2546+
[25] = PIN_FSCLKST_N, /* FSCLKST# */
2547+
[26] = RCAR_GP_PIN(1, 0), /* IRQ0 */
2548+
[27] = PIN_TRST_N, /* TRST# */
2549+
[28] = PIN_TCK, /* TCK */
2550+
[29] = PIN_TMS, /* TMS */
2551+
[30] = PIN_TDI, /* TDI */
2552+
[31] = RCAR_GP_PIN(2, 0), /* VI0_CLK */
2553+
} },
2554+
{ PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) {
2555+
[ 0] = RCAR_GP_PIN(2, 1), /* VI0_CLKENB */
2556+
[ 1] = RCAR_GP_PIN(2, 2), /* VI0_HSYNC# */
2557+
[ 2] = RCAR_GP_PIN(2, 3), /* VI0_VSYNC# */
2558+
[ 3] = RCAR_GP_PIN(2, 4), /* VI0_DATA0 */
2559+
[ 4] = RCAR_GP_PIN(2, 5), /* VI0_DATA1 */
2560+
[ 5] = RCAR_GP_PIN(2, 6), /* VI0_DATA2 */
2561+
[ 6] = RCAR_GP_PIN(2, 7), /* VI0_DATA3 */
2562+
[ 7] = RCAR_GP_PIN(2, 8), /* VI0_DATA4 */
2563+
[ 8] = RCAR_GP_PIN(2, 9), /* VI0_DATA5 */
2564+
[ 9] = RCAR_GP_PIN(2, 10), /* VI0_DATA6 */
2565+
[10] = RCAR_GP_PIN(2, 11), /* VI0_DATA7 */
2566+
[11] = RCAR_GP_PIN(2, 12), /* VI0_DATA8 */
2567+
[12] = RCAR_GP_PIN(2, 13), /* VI0_DATA9 */
2568+
[13] = RCAR_GP_PIN(2, 14), /* VI0_DATA10 */
2569+
[14] = RCAR_GP_PIN(2, 15), /* VI0_DATA11 */
2570+
[15] = RCAR_GP_PIN(2, 16), /* VI0_FIELD */
2571+
[16] = RCAR_GP_PIN(3, 0), /* VI1_CLK */
2572+
[17] = RCAR_GP_PIN(3, 1), /* VI1_CLKENB */
2573+
[18] = RCAR_GP_PIN(3, 2), /* VI1_HSYNC# */
2574+
[19] = RCAR_GP_PIN(3, 3), /* VI1_VSYNC# */
2575+
[20] = RCAR_GP_PIN(3, 4), /* VI1_DATA0 */
2576+
[21] = RCAR_GP_PIN(3, 5), /* VI1_DATA1 */
2577+
[22] = RCAR_GP_PIN(3, 6), /* VI1_DATA2 */
2578+
[23] = RCAR_GP_PIN(3, 7), /* VI1_DATA3 */
2579+
[24] = RCAR_GP_PIN(3, 8), /* VI1_DATA4 */
2580+
[25] = RCAR_GP_PIN(3, 9), /* VI1_DATA5 */
2581+
[26] = RCAR_GP_PIN(3, 10), /* VI1_DATA6 */
2582+
[27] = RCAR_GP_PIN(3, 11), /* VI1_DATA7 */
2583+
[28] = RCAR_GP_PIN(3, 12), /* VI1_DATA8 */
2584+
[29] = RCAR_GP_PIN(3, 13), /* VI1_DATA9 */
2585+
[30] = RCAR_GP_PIN(3, 14), /* VI1_DATA10 */
2586+
[31] = RCAR_GP_PIN(3, 15), /* VI1_DATA11 */
2587+
} },
2588+
{ PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) {
2589+
[ 0] = RCAR_GP_PIN(3, 16), /* VI1_FIELD */
2590+
[ 1] = RCAR_GP_PIN(4, 0), /* SCL0 */
2591+
[ 2] = RCAR_GP_PIN(4, 1), /* SDA0 */
2592+
[ 3] = RCAR_GP_PIN(4, 2), /* SCL1 */
2593+
[ 4] = RCAR_GP_PIN(4, 3), /* SDA1 */
2594+
[ 5] = RCAR_GP_PIN(4, 4), /* SCL2 */
2595+
[ 6] = RCAR_GP_PIN(4, 5), /* SDA2 */
2596+
[ 7] = RCAR_GP_PIN(1, 1), /* AVB0_RX_CTL */
2597+
[ 8] = RCAR_GP_PIN(1, 2), /* AVB0_RXC */
2598+
[ 9] = RCAR_GP_PIN(1, 3), /* AVB0_RD0 */
2599+
[10] = RCAR_GP_PIN(1, 4), /* AVB0_RD1 */
2600+
[11] = RCAR_GP_PIN(1, 5), /* AVB0_RD2 */
2601+
[12] = RCAR_GP_PIN(1, 6), /* AVB0_RD3 */
2602+
[13] = RCAR_GP_PIN(1, 7), /* AVB0_TX_CTL */
2603+
[14] = RCAR_GP_PIN(1, 8), /* AVB0_TXC */
2604+
[15] = RCAR_GP_PIN(1, 9), /* AVB0_TD0 */
2605+
[16] = RCAR_GP_PIN(1, 10), /* AVB0_TD1 */
2606+
[17] = RCAR_GP_PIN(1, 11), /* AVB0_TD2 */
2607+
[18] = RCAR_GP_PIN(1, 12), /* AVB0_TD3 */
2608+
[19] = RCAR_GP_PIN(1, 13), /* AVB0_TXCREFCLK */
2609+
[20] = RCAR_GP_PIN(1, 14), /* AVB0_MDIO */
2610+
[21] = RCAR_GP_PIN(1, 15), /* AVB0_MDC */
2611+
[22] = RCAR_GP_PIN(1, 16), /* AVB0_MAGIC */
2612+
[23] = RCAR_GP_PIN(1, 17), /* AVB0_PHY_INT */
2613+
[24] = RCAR_GP_PIN(1, 18), /* AVB0_LINK */
2614+
[25] = RCAR_GP_PIN(1, 19), /* AVB0_AVTP_MATCH */
2615+
[26] = RCAR_GP_PIN(1, 20), /* AVB0_AVTP_CAPTURE */
2616+
[27] = RCAR_GP_PIN(1, 21), /* CANFD0_TX_A */
2617+
[28] = RCAR_GP_PIN(1, 22), /* CANFD0_RX_A */
2618+
[29] = RCAR_GP_PIN(1, 23), /* CANFD1_TX */
2619+
[30] = RCAR_GP_PIN(1, 24), /* CANFD1_RX */
2620+
[31] = RCAR_GP_PIN(1, 25), /* CANFD_CLK */
2621+
} },
2622+
{ PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
2623+
[ 0] = RCAR_GP_PIN(5, 0), /* QSPI0_SPCLK */
2624+
[ 1] = RCAR_GP_PIN(5, 1), /* QSPI0_MOSI_IO0 */
2625+
[ 2] = RCAR_GP_PIN(5, 2), /* QSPI0_MISO_IO1 */
2626+
[ 3] = RCAR_GP_PIN(5, 3), /* QSPI0_IO2 */
2627+
[ 4] = RCAR_GP_PIN(5, 4), /* QSPI0_IO3 */
2628+
[ 5] = RCAR_GP_PIN(5, 5), /* QSPI0_SSL */
2629+
[ 6] = RCAR_GP_PIN(5, 6), /* QSPI1_SPCLK */
2630+
[ 7] = RCAR_GP_PIN(5, 7), /* QSPI1_MOSI_IO0 */
2631+
[ 8] = RCAR_GP_PIN(5, 8), /* QSPI1_MISO_IO1 */
2632+
[ 9] = RCAR_GP_PIN(5, 9), /* QSPI1_IO2 */
2633+
[10] = RCAR_GP_PIN(5, 10), /* QSPI1_IO3 */
2634+
[11] = RCAR_GP_PIN(5, 11), /* QSPI1_SSL */
2635+
[12] = RCAR_GP_PIN(5, 12), /* RPC_RESET# */
2636+
[13] = RCAR_GP_PIN(5, 13), /* RPC_WP# */
2637+
[14] = RCAR_GP_PIN(5, 14), /* RPC_INT# */
2638+
[15] = RCAR_GP_PIN(1, 26), /* DIGRF_CLKIN */
2639+
[16] = RCAR_GP_PIN(1, 27), /* DIGRF_CLKOUT */
2640+
[17] = SH_PFC_PIN_NONE,
2641+
[18] = SH_PFC_PIN_NONE,
2642+
[19] = SH_PFC_PIN_NONE,
2643+
[20] = SH_PFC_PIN_NONE,
2644+
[21] = SH_PFC_PIN_NONE,
2645+
[22] = SH_PFC_PIN_NONE,
2646+
[23] = SH_PFC_PIN_NONE,
2647+
[24] = SH_PFC_PIN_NONE,
2648+
[25] = SH_PFC_PIN_NONE,
2649+
[26] = SH_PFC_PIN_NONE,
2650+
[27] = SH_PFC_PIN_NONE,
2651+
[28] = SH_PFC_PIN_NONE,
2652+
[29] = SH_PFC_PIN_NONE,
2653+
[30] = SH_PFC_PIN_NONE,
2654+
[31] = SH_PFC_PIN_NONE,
2655+
} },
2656+
{ /* sentinel */ }
2657+
};
2658+
24992659
static const struct sh_pfc_soc_operations pinmux_ops = {
25002660
.pin_to_pocctrl = r8a77970_pin_to_pocctrl,
2661+
.get_bias = rcar_pinmux_get_bias,
2662+
.set_bias = rcar_pinmux_set_bias,
25012663
};
25022664

25032665
const struct sh_pfc_soc_info r8a77970_pinmux_info = {
@@ -2515,6 +2677,7 @@ const struct sh_pfc_soc_info r8a77970_pinmux_info = {
25152677
.nr_functions = ARRAY_SIZE(pinmux_functions),
25162678

25172679
.cfg_regs = pinmux_config_regs,
2680+
.bias_regs = pinmux_bias_regs,
25182681
.ioctrl_regs = pinmux_ioctrl_regs,
25192682

25202683
.pinmux_data = pinmux_data,

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