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Dinh Nguyenbebarino
Dinh Nguyen
authored and
bebarino
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clk: socfpga: Convert to s10/agilex/n5x to use clk_hw
As recommended by Stephen Boyd, convert the Agilex/Stratix10/n5x clock driver to use the clk_hw registration method. Suggested-by: Stephen Boyd <[email protected]> Signed-off-by: Dinh Nguyen <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
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-147
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6 files changed

+159
-147
lines changed

‎drivers/clk/socfpga/clk-agilex.c

Lines changed: 60 additions & 54 deletions
Original file line numberDiff line numberDiff line change
@@ -303,75 +303,75 @@ static const struct stratix10_gate_clock agilex_gate_clks[] = {
303303
static int n5x_clk_register_c_perip(const struct n5x_perip_c_clock *clks,
304304
int nums, struct stratix10_clock_data *data)
305305
{
306-
struct clk *clk;
306+
struct clk_hw *hw_clk;
307307
void __iomem *base = data->base;
308308
int i;
309309

310310
for (i = 0; i < nums; i++) {
311-
clk = n5x_register_periph(&clks[i], base);
312-
if (IS_ERR(clk)) {
311+
hw_clk = n5x_register_periph(&clks[i], base);
312+
if (IS_ERR(hw_clk)) {
313313
pr_err("%s: failed to register clock %s\n",
314314
__func__, clks[i].name);
315315
continue;
316316
}
317-
data->clk_data.clks[clks[i].id] = clk;
317+
data->clk_data.hws[clks[i].id] = hw_clk;
318318
}
319319
return 0;
320320
}
321321

322322
static int agilex_clk_register_c_perip(const struct stratix10_perip_c_clock *clks,
323323
int nums, struct stratix10_clock_data *data)
324324
{
325-
struct clk *clk;
325+
struct clk_hw *hw_clk;
326326
void __iomem *base = data->base;
327327
int i;
328328

329329
for (i = 0; i < nums; i++) {
330-
clk = s10_register_periph(&clks[i], base);
331-
if (IS_ERR(clk)) {
330+
hw_clk = s10_register_periph(&clks[i], base);
331+
if (IS_ERR(hw_clk)) {
332332
pr_err("%s: failed to register clock %s\n",
333333
__func__, clks[i].name);
334334
continue;
335335
}
336-
data->clk_data.clks[clks[i].id] = clk;
336+
data->clk_data.hws[clks[i].id] = hw_clk;
337337
}
338338
return 0;
339339
}
340340

341341
static int agilex_clk_register_cnt_perip(const struct stratix10_perip_cnt_clock *clks,
342342
int nums, struct stratix10_clock_data *data)
343343
{
344-
struct clk *clk;
344+
struct clk_hw *hw_clk;
345345
void __iomem *base = data->base;
346346
int i;
347347

348348
for (i = 0; i < nums; i++) {
349-
clk = s10_register_cnt_periph(&clks[i], base);
350-
if (IS_ERR(clk)) {
349+
hw_clk = s10_register_cnt_periph(&clks[i], base);
350+
if (IS_ERR(hw_clk)) {
351351
pr_err("%s: failed to register clock %s\n",
352352
__func__, clks[i].name);
353353
continue;
354354
}
355-
data->clk_data.clks[clks[i].id] = clk;
355+
data->clk_data.hws[clks[i].id] = hw_clk;
356356
}
357357

358358
return 0;
359359
}
360360

361361
static int agilex_clk_register_gate(const struct stratix10_gate_clock *clks, int nums, struct stratix10_clock_data *data)
362362
{
363-
struct clk *clk;
363+
struct clk_hw *hw_clk;
364364
void __iomem *base = data->base;
365365
int i;
366366

367367
for (i = 0; i < nums; i++) {
368-
clk = s10_register_gate(&clks[i], base);
369-
if (IS_ERR(clk)) {
368+
hw_clk = s10_register_gate(&clks[i], base);
369+
if (IS_ERR(hw_clk)) {
370370
pr_err("%s: failed to register clock %s\n",
371371
__func__, clks[i].name);
372372
continue;
373373
}
374-
data->clk_data.clks[clks[i].id] = clk;
374+
data->clk_data.hws[clks[i].id] = hw_clk;
375375
}
376376

377377
return 0;
@@ -380,18 +380,18 @@ static int agilex_clk_register_gate(const struct stratix10_gate_clock *clks,
380380
static int agilex_clk_register_pll(const struct stratix10_pll_clock *clks,
381381
int nums, struct stratix10_clock_data *data)
382382
{
383-
struct clk *clk;
383+
struct clk_hw *hw_clk;
384384
void __iomem *base = data->base;
385385
int i;
386386

387387
for (i = 0; i < nums; i++) {
388-
clk = agilex_register_pll(&clks[i], base);
389-
if (IS_ERR(clk)) {
388+
hw_clk = agilex_register_pll(&clks[i], base);
389+
if (IS_ERR(hw_clk)) {
390390
pr_err("%s: failed to register clock %s\n",
391391
__func__, clks[i].name);
392392
continue;
393393
}
394-
data->clk_data.clks[clks[i].id] = clk;
394+
data->clk_data.hws[clks[i].id] = hw_clk;
395395
}
396396

397397
return 0;
@@ -400,64 +400,49 @@ static int agilex_clk_register_pll(const struct stratix10_pll_clock *clks,
400400
static int n5x_clk_register_pll(const struct stratix10_pll_clock *clks,
401401
int nums, struct stratix10_clock_data *data)
402402
{
403-
struct clk *clk;
403+
struct clk_hw *hw_clk;
404404
void __iomem *base = data->base;
405405
int i;
406406

407407
for (i = 0; i < nums; i++) {
408-
clk = n5x_register_pll(&clks[i], base);
409-
if (IS_ERR(clk)) {
408+
hw_clk = n5x_register_pll(&clks[i], base);
409+
if (IS_ERR(hw_clk)) {
410410
pr_err("%s: failed to register clock %s\n",
411411
__func__, clks[i].name);
412412
continue;
413413
}
414-
data->clk_data.clks[clks[i].id] = clk;
414+
data->clk_data.hws[clks[i].id] = hw_clk;
415415
}
416416

417417
return 0;
418418
}
419419

420-
static struct stratix10_clock_data *__socfpga_agilex_clk_init(struct platform_device *pdev,
421-
int nr_clks)
420+
static int agilex_clkmgr_init(struct platform_device *pdev)
422421
{
423422
struct device_node *np = pdev->dev.of_node;
424423
struct device *dev = &pdev->dev;
425424
struct stratix10_clock_data *clk_data;
426-
struct clk **clk_table;
427425
struct resource *res;
428426
void __iomem *base;
429-
int ret;
427+
int i, num_clks;
430428

431429
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
432430
base = devm_ioremap_resource(dev, res);
433431
if (IS_ERR(base))
434-
return ERR_CAST(base);
435-
436-
clk_data = devm_kzalloc(dev, sizeof(*clk_data), GFP_KERNEL);
437-
if (!clk_data)
438-
return ERR_PTR(-ENOMEM);
432+
return PTR_ERR(base);
439433

440-
clk_data->base = base;
441-
clk_table = devm_kcalloc(dev, nr_clks, sizeof(*clk_table), GFP_KERNEL);
442-
if (!clk_table)
443-
return ERR_PTR(-ENOMEM);
444-
445-
clk_data->clk_data.clks = clk_table;
446-
clk_data->clk_data.clk_num = nr_clks;
447-
ret = of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data->clk_data);
448-
if (ret)
449-
return ERR_PTR(ret);
434+
num_clks = AGILEX_NUM_CLKS;
450435

451-
return clk_data;
452-
}
436+
clk_data = devm_kzalloc(dev, struct_size(clk_data, clk_data.hws,
437+
num_clks), GFP_KERNEL);
438+
if (!clk_data)
439+
return -ENOMEM;
453440

454-
static int agilex_clkmgr_init(struct platform_device *pdev)
455-
{
456-
struct stratix10_clock_data *clk_data;
441+
for (i = 0; i < num_clks; i++)
442+
clk_data->clk_data.hws[i] = ERR_PTR(-ENOENT);
457443

458-
clk_data = __socfpga_agilex_clk_init(pdev, AGILEX_NUM_CLKS);
459-
if (IS_ERR(clk_data))
460-
return PTR_ERR(clk_data);
444+
clk_data->base = base;
445+
clk_data->clk_data.num = num_clks;
461446

462447
agilex_clk_register_pll(agilex_pll_clks, ARRAY_SIZE(agilex_pll_clks), clk_data);
463448

@@ -470,16 +455,36 @@ static int agilex_clkmgr_init(struct platform_device *pdev)
470455

471456
agilex_clk_register_gate(agilex_gate_clks, ARRAY_SIZE(agilex_gate_clks),
472457
clk_data);
458+
of_clk_add_hw_provider(np, of_clk_hw_onecell_get, &clk_data->clk_data);
473459
return 0;
474460
}
475461

476462
static int n5x_clkmgr_init(struct platform_device *pdev)
477463
{
464+
struct device_node *np = pdev->dev.of_node;
465+
struct device *dev = &pdev->dev;
478466
struct stratix10_clock_data *clk_data;
467+
struct resource *res;
468+
void __iomem *base;
469+
int i, num_clks;
470+
471+
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
472+
base = devm_ioremap_resource(dev, res);
473+
if (IS_ERR(base))
474+
return PTR_ERR(base);
475+
476+
num_clks = AGILEX_NUM_CLKS;
477+
478+
clk_data = devm_kzalloc(dev, struct_size(clk_data, clk_data.hws,
479+
num_clks), GFP_KERNEL);
480+
if (!clk_data)
481+
return -ENOMEM;
482+
483+
for (i = 0; i < num_clks; i++)
484+
clk_data->clk_data.hws[i] = ERR_PTR(-ENOENT);
479485

480-
clk_data = __socfpga_agilex_clk_init(pdev, AGILEX_NUM_CLKS);
481-
if (IS_ERR(clk_data))
482-
return PTR_ERR(clk_data);
486+
clk_data->base = base;
487+
clk_data->clk_data.num = num_clks;
483488

484489
n5x_clk_register_pll(agilex_pll_clks, ARRAY_SIZE(agilex_pll_clks), clk_data);
485490

@@ -492,6 +497,7 @@ static int n5x_clkmgr_init(struct platform_device *pdev)
492497

493498
agilex_clk_register_gate(agilex_gate_clks, ARRAY_SIZE(agilex_gate_clks),
494499
clk_data);
500+
of_clk_add_hw_provider(np, of_clk_hw_onecell_get, &clk_data->clk_data);
495501
return 0;
496502
}
497503

‎drivers/clk/socfpga/clk-gate-s10.c

Lines changed: 9 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -65,12 +65,13 @@ static const struct clk_ops dbgclk_ops = {
6565
.get_parent = socfpga_gate_get_parent,
6666
};
6767

68-
struct clk *s10_register_gate(const struct stratix10_gate_clock *clks, void __iomem *regbase)
68+
struct clk_hw *s10_register_gate(const struct stratix10_gate_clock *clks, void __iomem *regbase)
6969
{
70-
struct clk *clk;
70+
struct clk_hw *hw_clk;
7171
struct socfpga_gate_clk *socfpga_clk;
7272
struct clk_init_data init;
7373
const char *parent_name = clks->parent_name;
74+
int ret;
7475

7576
socfpga_clk = kzalloc(sizeof(*socfpga_clk), GFP_KERNEL);
7677
if (!socfpga_clk)
@@ -112,10 +113,12 @@ struct clk *s10_register_gate(const struct stratix10_gate_clock *clks, void __io
112113
init.parent_data = clks->parent_data;
113114
socfpga_clk->hw.hw.init = &init;
114115

115-
clk = clk_register(NULL, &socfpga_clk->hw.hw);
116-
if (WARN_ON(IS_ERR(clk))) {
116+
hw_clk = &socfpga_clk->hw.hw;
117+
118+
ret = clk_hw_register(NULL, &socfpga_clk->hw.hw);
119+
if (ret) {
117120
kfree(socfpga_clk);
118-
return NULL;
121+
return ERR_PTR(ret);
119122
}
120-
return clk;
123+
return hw_clk;
121124
}

‎drivers/clk/socfpga/clk-periph-s10.c

Lines changed: 24 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -93,14 +93,15 @@ static const struct clk_ops peri_cnt_clk_ops = {
9393
.get_parent = clk_periclk_get_parent,
9494
};
9595

96-
struct clk *s10_register_periph(const struct stratix10_perip_c_clock *clks,
96+
struct clk_hw *s10_register_periph(const struct stratix10_perip_c_clock *clks,
9797
void __iomem *reg)
9898
{
99-
struct clk *clk;
99+
struct clk_hw *hw_clk;
100100
struct socfpga_periph_clk *periph_clk;
101101
struct clk_init_data init;
102102
const char *name = clks->name;
103103
const char *parent_name = clks->parent_name;
104+
int ret;
104105

105106
periph_clk = kzalloc(sizeof(*periph_clk), GFP_KERNEL);
106107
if (WARN_ON(!periph_clk))
@@ -118,23 +119,25 @@ struct clk *s10_register_periph(const struct stratix10_perip_c_clock *clks,
118119
init.parent_data = clks->parent_data;
119120

120121
periph_clk->hw.hw.init = &init;
122+
hw_clk = &periph_clk->hw.hw;
121123

122-
clk = clk_register(NULL, &periph_clk->hw.hw);
123-
if (WARN_ON(IS_ERR(clk))) {
124+
ret = clk_hw_register(NULL, hw_clk);
125+
if (ret) {
124126
kfree(periph_clk);
125-
return NULL;
127+
return ERR_PTR(ret);
126128
}
127-
return clk;
129+
return hw_clk;
128130
}
129131

130-
struct clk *n5x_register_periph(const struct n5x_perip_c_clock *clks,
132+
struct clk_hw *n5x_register_periph(const struct n5x_perip_c_clock *clks,
131133
void __iomem *regbase)
132134
{
133-
struct clk *clk;
135+
struct clk_hw *hw_clk;
134136
struct socfpga_periph_clk *periph_clk;
135137
struct clk_init_data init;
136138
const char *name = clks->name;
137139
const char *parent_name = clks->parent_name;
140+
int ret;
138141

139142
periph_clk = kzalloc(sizeof(*periph_clk), GFP_KERNEL);
140143
if (WARN_ON(!periph_clk))
@@ -151,23 +154,25 @@ struct clk *n5x_register_periph(const struct n5x_perip_c_clock *clks,
151154
init.parent_names = parent_name ? &parent_name : NULL;
152155

153156
periph_clk->hw.hw.init = &init;
157+
hw_clk = &periph_clk->hw.hw;
154158

155-
clk = clk_register(NULL, &periph_clk->hw.hw);
156-
if (WARN_ON(IS_ERR(clk))) {
159+
ret = clk_hw_register(NULL, hw_clk);
160+
if (ret) {
157161
kfree(periph_clk);
158-
return NULL;
162+
return ERR_PTR(ret);
159163
}
160-
return clk;
164+
return hw_clk;
161165
}
162166

163-
struct clk *s10_register_cnt_periph(const struct stratix10_perip_cnt_clock *clks,
167+
struct clk_hw *s10_register_cnt_periph(const struct stratix10_perip_cnt_clock *clks,
164168
void __iomem *regbase)
165169
{
166-
struct clk *clk;
170+
struct clk_hw *hw_clk;
167171
struct socfpga_periph_clk *periph_clk;
168172
struct clk_init_data init;
169173
const char *name = clks->name;
170174
const char *parent_name = clks->parent_name;
175+
int ret;
171176

172177
periph_clk = kzalloc(sizeof(*periph_clk), GFP_KERNEL);
173178
if (WARN_ON(!periph_clk))
@@ -195,11 +200,12 @@ struct clk *s10_register_cnt_periph(const struct stratix10_perip_cnt_clock *clks
195200
init.parent_data = clks->parent_data;
196201

197202
periph_clk->hw.hw.init = &init;
203+
hw_clk = &periph_clk->hw.hw;
198204

199-
clk = clk_register(NULL, &periph_clk->hw.hw);
200-
if (WARN_ON(IS_ERR(clk))) {
205+
ret = clk_hw_register(NULL, hw_clk);
206+
if (ret) {
201207
kfree(periph_clk);
202-
return NULL;
208+
return ERR_PTR(ret);
203209
}
204-
return clk;
210+
return hw_clk;
205211
}

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